The Verification Of AES Serial Communication Security IP Based On UVM

With the development of the manufacture and design techniques,the amount of work and resource needed for verification increase rapidly as the complexity and capacity of the chips increase meanwhile.As a key step in chip development,verification takes about 70% of the total R&D process,and it plays a decisive role in chip performance,tapeout effect,and development cost.Traditional verification methods have been difficult to meet the needs of chip verification.UVM(Universal Verification Methodology)has improved the traditional verification methods.Its verification platform is more feasible to duplicate with more layers and functions of reutilization.The use of UVM technology to build a verification platform has become a trend in the IC design industry.Based on the in-depth study of the verification language System Verilog and the verification methodology UVM,this thesis aims to create the high reusability platform,improve the verification adequacy and efficiency,and carry out verification work on the AES serial communication security IP of the internship project to ensure defective rate meet the requirement of manufacture.The main work of the thesis is as follows:This thesis first analyzes the AES algorithm and asynchronous serial communication protocol,and studies the overall structure of the AES serial communication security IP,as well as the functions and implementation methods of each internal module.On this basis,the verification plan for the AES serial communication security IP was developed,and the design of the test method,coverage strategy and the extraction of test function points were completed.Then,according to the extracted function points,test cases such as interface verification,abnormal register access verification,encryption and decryption function verification,and injection error transmission verification were developed.Finally,this thesis uses SV and UVM to complete the hierarchical creation of the verification platform,and design verification components,including the incentive drive component,the monitoring design response component,the package container component,the result verification component,the simulating design work process component,the evaluating verification result component,etc.In the process of building the verification platform,the factory mechanism is used to complete the registration of verification components and variables,and the reuse of components is realized by modifying and replacing the kernel functions,which enhances the reusability of the platform.The sequence mechanism is used to generate directional incentives and random incentives.By separating the incentives and the platform,the error probability of the platform is reduced,and the stability of the platform is increased.TLM mechanism is used to realize platform communication and improve the flexibility of the platform.Scripts are used to realize the automatic creation of verification components and the operation control of the platform,which improves the efficiency of verification.After the verification platform has been built,the verification under different verification scenarios is completed through the incentive group test.On this basis,assertion timing verification and system-level verification are added,and the prototype verification is completed by using the FPGA board,which improves the completeness and adequacy of verification.According to the results of the coverage report feedback,the constraint range of the test cases is confined,and directional incentives are added.In the end,the function coverage reached 100%,and the code coverage reached more than 99%,which met the expected goal of verification.