Research On Verification IP Based On UVM For Serial Synchronus Two-Wire Bus

With the increasing complexity of digital integrated circuits and SoC systems design,fast and reliable verification of SoC systems becomes more and more important.At the same time,the requirements of various peripheral devices,higher speed,lower power consumption,configurable,and expandable,have been proposed for the bus.Among them,the serial synchronous two-wire bus I2 C and its derivative bus are widely used in various products due to their convenient use,low power consumption and strong anti-interference ability.However,these buses do not have a common verification IP for verification.And by building a verification platform separately,it will cause a lot of repetitive work and low efficiency,and lead to many verification components which are difficult to maintain,transplant and reuse.At the same time,the differences in test cases and self-test mechanisms of different buses cannot ensure the completeness of verification,so it is necessary to study a universal serial synchronous two-wire bus verification IP.This thesis studies and analyzes the commonalities of the serial synchronous two-wire bus protocols such as the standard I2C(including the upgraded ultra-fast mode),customed I2 C,and I3 C buses.There are similar characteristics of the verification components in dual lines,data composition,read and write operations,etc.And the differences are in the bus width,transmission data format,and the composition of operation sequences in the sequence.Therefore,based on the Universal Verification Method(UVM),a universal serial synchronous two-wire bus verification IP is proposed by using parameterization to construct a verification component.The parameterized verification component can realize the requirements of configurability and reusability,and the self-check mechanism and function coverage group can realize the completeness requirement of the coverageoriented serial synchronous two-wire communication bus verification.At the same time,three modules are proposed to solve the shortcomings of the existing platform architecture: for the difficulties of reusing the module-level at the system level,a protection module is proposed;for the difficulties of synchronization processing in the multi-verification environment,a common module is proposed;for error injection,a error bus module is proposed without changing the verification component.For the constructed universal serial synchronous two-wire bus verification IP,two typical SoC system chips are used to verify its vertical multiplexability in the same SoC system and horizontal multiplexability between different SoC systems.Experimental results show that the serial synchronous two-wire bus verification IP can be used to quickly build a verification environment which is similar to the I2 C bus data format.The random test cases oriented to coverage can quickly get nearly 100% coverage,and the self-check mechanism can jointly ensure the completeness of the verification.The verification IP can be easily reused from the verification environment of the submodule to the verification of the SoC system,and can also be multiplexed into different SoC systems,so the verification time can be minimized and verification efficiency can be improved.