Research And Implementation Of Encryption System Based On Asymmetric Encryption Algorithm

Cryptography technology provides strong support for ensuring information security.Cryptography technology can not only perform functions such as digital signature verification,identity verification,system security,and etc,but also ensure the integrity and accuracy of information,thereby preventing information from being leaked,tampered,forged and counterfeited.The core technology of cryptography is encryption and decryption algorithms.According to the different forms of key,encryption algorithm includes symmetric encryption and asymmetric encryption.Symmetric encryption uses the same key during encryption and decryption.And asymmetric encryption uses the public key during encryption,and the private key during decryption.However,the traditional software implementation of cryptographic algorithm requires low cost,its operational speed,security coefficient,and stability are not a quarter as good as hardware.So the hardware implementation of SM2 and RSA algorithm produce significant impacts both in academic and application areas.Analyzing the theoretical basis and implementation algorithms of the SM2 and RSA algorithms,we can know that the point multiplication is the core of the SM2,and the modular power is the center of the RSA.Decomposing these two operations,it can be concluded that only by breaking through the common bottleneck of multiplication can the operation speed be improved.In terms of algorithm,for RSA,the modular power is implemented by R-L binary expansion method combining randomization and pseudo operations,and modular multiplication is implemented by an improved 256-bit high-speed Montgomery method.For SM2,256-bit prime number elliptic curve parameters are used.The point multiplication operation is implemented by a multi scalar multiplication method combining randomization key and window width 3 and 2.Point double and point add is completed in Jacobian coordinates and affine coordinates.In modulus operation,the modular multiplication is implemented by the form of large number multiplication and modular reduction,the modular inversion uses the binary Euclidean inversion method.In terms of hardware design,firstly,the overall system architecture is designed based on SM2 and RSA algorithm architecture.Then the pipeline and modular design are used to optimize and improve the hardware structure by means of separation and sharing of modules and data channels.Finally,the Verilog is selected to complete the RTL for each module according to the improved algorithm.In addition,considering to the hardware resources and computing speed,the module reduction is designed according to the recommended SM2 module.At the same time,the structure of shared multiplier for SM2 and RSA is proposed.Only one 66 bit multiplier and four 512 bit adders need to be instantiated,and 256 bit multiplication can be completed in 9 cycles of serial calculation.After completing the hardware design of the system,an efficient and reusable verification platform for the system is established based on the System Verilog and UVM verification methodology.With the help of this platform,this article chooses a method of random test and directional test to verify the function of the system.As a result,it has achieved a code coverage of over 94% and a functional coverage of 100%,which meets the expected requirements.Finally,under the SMIC 0.13 ?m process environment,the DC synthesis of the system is completed,and the comprehensive area is about 352.5k gates.At 100 MHz hardware clock,the system needs about 9.18 ms to complete 1024 bit modular power and the throughput rate is 109 Kbps.It takes about 306?s to complete 256 bit point multiplication and the throughput rate is 817.5Kbps.Compared with other similar designs,this system has excellent performance and great advantages.