Asynchronous Serial Communication Module Hard Ip Core Design And Verification

This thesis presents a hard IP core of UART in a 0.35μm SiGe CMOS process. Semi-customized technology is used and the design flow includes physical synthesis, physical design, verification, power analysis and optimization.Serial communication reduces the distortion of the signal, therefore makes data transfer between two systems separated in great distance possible. A universal asynchronous receiver/ transmitter (UART) is an integrated circuit used for serial communication, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter). It handles the conversion between serial and parallel data. It also can be used as a hard intellectual property core for the microprocessor interface.With the technology scaling as well as the increasing complexity of modern digital integrated circuits, interconnect effects play an increasingly important role in determining design methodologies. Physical synthesis methodology is used to solve the problem that the precision of wire-loads model will be decreased as the ASIC designs move into the deep-submicrometer process era. The limitations of logic synthesis in the traditional design flow are analyzed and how the efficacy of interconnect estimation improves with the availability of physical information is showed.In VLSI design, physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. An ASIC prototype of UART hard IP core has been designed in a four metal layer CMOS process. After the placement of cells, the clock tree is inserted in the design by the layout tool. After detailed route is complete, the real timing delays of the chip are extracted, and plugged into PrimeTime for analysis. If the design passes static timing analysis, it is ready to undergo LVS (layout versus schematic) and DRC (design rule checking) before tape-out.Functional validation and simulations constitute a large part of the entire ASIC design process and schedule. The verification of the whole UART IP core can be divided into two categories: dynamic simulation and static verification. Bus Function Model (BFM) is used in the dynamic simulation to simulate the interface of the UART module. Static verification including formal verification and static timing analysis (STA) for thedesign of UART ASIC is presented. Formal verification is a mathematical method used to directly compare the logical function of one design with that of another. The static timing analysis, to some extent, is the most important step in the whole ASIC design process. The static timing analysis is performed both for the pre and post-layout gate-level netlist.Power reduction is rapidly becoming an important design goal. Designers are moving to incorporate power considerations into all phases of their design flow. All components of power are modeled. The power analysis results with synopsys EDATools Power Compiler and Nanosim are discussed.The delay analysis for the critical path is about 8.4ns, the average power consumption is about 7mW at the frequency of 50MHz and the area of the core is about 0.18mm~2. The whole area adding the PAD for test of the chip is about 0.8mm~2.