Design And Verification Of EEPROM Based On IIC

Since the twenty-first Century,with the rapid development of microelectronic technology and the improvement of consumers' living standard,portable consumer electronic products have appeared in all aspects of people's life.Semiconductor memory devices are the most critical components to ensure their normal operation.Serial EEPROM plays an important role in this field because of its few interfaces,simple structure,reliable storage,low power consumption and low price.The IIC(Inter-Integrated Circuit,IC bus)bus designed by PHILPS has simple structure.It can realize data transmission between devices on the bus only by clock line and data line,and can avoid the shortcomings of addressing between traditional devices.Based on the above characteristics,serial EEPROM based on IIC bus is widely used in smart electronic locks,IC cards and other portable consumer electronics products.The work of this paper mainly includes the design of serial EEPROM and verification based on UVM platform.The design part of this paper is based on the introduction of serial EEPROM timing characteristics and reading and writing functions according to Atmel company's data manual AT24HC02 C.the functional structure of this circuit is divided.Including the CORE layer is the focus of this design research,it is a major function of the chip set,including the realization of the peripheral control logic block and EEPROM IP module implementation to realize serial EEPROM read and write operations,after completing the Verilog design of main modules,using modelsim software of circuit design has carried on the simple analysis of the simulation.The verification part is to use the UVM platform for functional verification of the design.On the design of architecture,function and interface characteristics on the basis of in-depth analysis,formulated the validation plan,according to the data in the manual is introduced and the result of the test,to extract the feature points,determine the UVM verification platform architecture,and uses the System Verilog language realization of various components of the platform,then write effective and effective incentives on the verification platform for simulation,and obtain simulation waveforms.The analysis of simulation results shows that the verification results are in line with the verification plan.The code coverage rate is more than 90%,indicating that the design code has realized the maximum utilization,and the functional coverage rate has reached 100%,meeting the comprehensive requirements of function point inspection.The platform can effectively improve the verification efficiency,reduce the possibility of a leak in the design process,at the same time,the verification platform to project the future chip verification work provides a good reference.