The Verification Of EECTRL Based On VMM And The Analysis Of Coverage Report

With the development of the SOC and IP technology, the technology of design and technology of verification are also developed. The technology of SOC decreases the time range from the design of circuit to the market. When we finish the whole flow, the verification takes up about70%of the whole design time. But the design which is not so prefect mainly caused the failure when the design tapes out. So verification is a very important part of the whole flow. The key point of this paper is how to build a verification environment based on VMM and to complete the work of the verification due to the analysis of the coverage report.A block level verification environment for an EEPROM interface circuit is built in this paper. VMM is used when building the environment. This verification methodology is based on System Verilog. The environment is built with different layers. Constrained random stimulus is generated in generator. At last the coverage report is generated. New cases are added due to the analysis of the coverage report. This paper makes a specific description of how to build an environment platform for the EEPROM interface.A reused verification platform is built.After the simulation,coverage report is analysed and new cases are added.This paper also makes a short description of the EEPROM interface circuit. The advantage of VMM is showed during the description of how to build a VMM environment. The coverage is improved during the simulation of the design and debug of RTL code. The code coverage and function coverage reach100%.The FSM reaches71.43%,which is confirmed by the designer. Then the goal of the verification is reached in this paper.