CBUS Verification Platform Based On UVM

With the continuous development of the integrated circuit industry,integrated circuit design is becoming more and more complex,the scale of the chip is increasing proportionally,and the number of IP(Intellectual Property)cores on each chip is increasing,it also bringing challenges in quality assurance and cycle of IC(Integrated Circuit)design.Verification is a crucial step in the IC design,which is related to the success of tape-out,but the traditional verification method can not meet the requirements of present chip verification scale,verification that it takes about 70% of the total chip cycle,it can be said that most of the time in the chip design is verification,therefore,improving the verification method is an urgent need to shorten the entire chip cycle and reduce the cost of the chip.In recent years,the UVM(Universal Verification Methodology)not only overcomes the shortcomings of traditional verification methods,but also has obvious advantages in setting up the verification environment,it has gradually replaced VMM(Verification Methodology Manual).The paper will mainly introduce the construction of verification environment based on UVM advanced verification method.Compared to system verilog,UVM is a more advanced verification method,which solves many problems that system verilog cannot solve,such as multiple components in a verification platform,the function of these components,and how they communicate with each other and so on.UVM also integrates all the advantages of OVM(Open Verification Methodology)and VMM,including OVM's factory mechanism,and VMM's register solution,and has reusability and portability features,shortening the period for building verification platforms,and thus more time can be used to write test cases.In addition,UVM also encapsulates many methods,in the process of building a UVM platform,reduceing the probability of error in the verification platform and the debugging time,thereby,shortening the verification period and improving the verification efficiency.Based on the many advantages of UVM,this verification method has been supported by many IC design vendors,including the three major EDA(Electronic Design Automation)vendors.This paper will build a verification platform based on the UVM verification method and according to the author's actual work project,CBUS(a kind of BUS)protocol,verify the DUT(Design Under Test),analyze the simulation results,modify the design under test,sothat the DUT can be optimized.First,interpret the CBUS protocol,use verilog to write RTL(Register Transistor Logic)code,then build a UVM verification platform,write test cases,verify the DUT,and finally verify the correctness and integrity of the DUT through code coverage and functional coverage,implementing the optimized DUT.In the process of building a UVM verification platform,first you need to analyze the CBUS protocol in detail,then draw the framework diagram of the entire verification platform,and then model each component to realize the entire verification platform.When collecting the function coverage,it is necessary to divide the function points according to the specifications of the CBUS protocol,so as to ensure the function coverage is complete and effective.The design is simulated by VCS(Verilog Compile Simulation),analyzed the simulation results,and then modified the design,and increased the test incentive,finally,which code coverage and functional coverage finally achieves 100%,it verifies the correctness and functional completeness of the DUT,and also proves that the application of the UVM verification method to build the verification platform actually shorten the verification cycle and reduce the cost.