Study And Implementation Of Synchronization Algorithm In Multi-mode Digital Modulation Signal Demodulation

Beginning in the 1970 s,the communications industry has gradually changed from an analog communications system to a digital communications system.The system and standards of communications have been rapidly developed and improved,and the scope of communications services has become more extensive.As demand increases and spectrum resources become more and more tense,multi-standard digital modulation signals are gradually being widely used.Multi-standard modulation signal demodulation synchronization algorithm has gradually become a research hotspot in the field of communications.In the field of modern communication applications,the communication environment is complex,modulation and demodulation are an important part of the digital communication system,and the performance directly affects the communication quality.In order to achieve accurate demodulation of the received signal,a high-precision,real-time,and fast demodulation algorithm is essential.In this paper,a detailed theoretical study of the synchronization algorithm of the digital demodulation system is carried out,and the characteristics of QPSK,OQPSK and low-order QAM modulation signals are improved,and the research and implementation of the synchronization algorithm in the modulation signal demodulation are further completed.Carrier synchronization is divided into two parts: carrier frequency synchronization and carrier phase synchronization.Open-loop carrier synchronization algorithms such as FFT frequency offset estimation algorithm,Viterbi frequency offset estimation algorithm and Viterbi phase offset estimation algorithm are analyzed in detail,as well as closed loop carrier synchronization algorithm based on phase-locked loop.Then use MATLAB to model and simulate the algorithm.In the open-loop algorithm,the simulation analysis is performed on the accuracy and the carrier deviation estimation range of the algorithm.In the closed-loop algorithm,the simulation analysis is performed on the loop convergence speed.Through the comparison and analysis of carrier synchronization algorithms,combined with actual applications,a two-level carrier synchronization design is adopted and simulated.The simulation results show that the design frequency offset estimation range is larger and the loop convergence speed is faster.In terms of timing synchronization technology,this paper has conducted detailed research on different timing error estimation algorithms,including maximum average power algorithm,nonlinear timing error estimation algorithm and Gardner timing error estimation algorithm.Modeling and simulating the algorithm through MATLAB,mainly analyzes the stability,accuracy and loop convergence speed of the closed-loop algorithm.Finally,combined with the actual application and through the simulation results of the algorithm's bit error rate,a comparative analysis of different bit timing algorithms is carried out to verify the effectiveness and feasibility of the algorithm.At the end of the paper,the hardware test platform is introduced first,and then the synchronization algorithm is logically implemented and functionally tested according to the project requirements.For the carrier synchronization algorithm,two-level carrier synchronization algorithm is used,and the detailed process of the algorithm implementation is given.Model Sim is used to simulate the carrier synchronization of QPSK,OQPSK and16 QAM signals,and the synchronization results are carried out through MATLAB.Analysis shows that the carrier synchronization module can estimate and compensate the carrier error of the above-mentioned signal.For the timing synchronization algorithm,the design adopts the Gardner timing synchronization loop,and the algorithm is appropriately improved,which is easier to implement in engineering.The detailed implementation process of the algorithm is given,and the functional simulation is carried out through Model Sim,and the data is analyzed in combination with MATLAB.The synchronization module completes the timing synchronization of the signal very well.When the XCKU085 T FFG1157-2I chip is used in the design,the overall DSP consumption of the system is 67%,the dynamic power consumption is 4.608 W,and the static power consumption is 1.639 W.