Research On Synchronization Technology Of Data Transmission And The Relization Of High-Speed Interface Design

Synchronization is a challenging and important task in digital communication. Receiver performance of demodulation system is directly dependent on the synchronization performance. Synchronization technology mainly consist of carrier synchronization and timing synchronization. As the foundation of coherent demodulation, carrier synchronization is a process acquiring a carrier that has the same frequency and phase as the receive signals in the receiver. Timing synchronization is a problem facing with all the demodulation technology, which is the process of extracting symbol timing information with a frequency same as code rate and a phase same as the optimum sampling decision time from received baseband signals. This paper has a deep analysis of the synchronization algorithms of Multiple Phase Shift Keying(MPSK) and Continuous Phase Modulation(CPM).Firstly, the basic theory of phase-locked loop is introduced in this paper. For MPSK signal, we mainly analysis the structure of closed loop synchronous which is based on phase-locked loop. Carrier synchronization mainly discusses the classical structure of Costas loop. While timing synchronization discusses the Gardner synchronization algorithm which is based on phase-locked loop and independent of the carrier phase. Aim to the above two algorithms, we put forward a synchronous demodulation scheme with the base of Costas carrier recovery with the help of Gardner loop and have a simulation of the synchronization performance about BPSK, QPSK and 8PSK respectively. Because of the nonlinear of modulation in CPM signal, the main research is some open loop synchronization algorithm based on data-help. For carrier synchronization, we introduce some classical frequency estimation algorithms such as Kay, L&R and Fitz, and put forward a GMSK carrier estimation algorithm with the pilot sequence all of 1 and have simulation of the above algorithms. In the timing synchronization, our research is focused on the method of using the PN code that has a good correlation as the pre-code and proved that it can acquire good synchronization performance by using PN code as the timing synchronization code of GMSK signal by simulation. At the end of the paper, in order to achieve the integration of digital board and upper machine, and make the transmission of the synchronization information from FPGA to upper machine in time, we design the high speed ethernet front-end ports based on FPGA with the data transmission rate upping to G level.