Research And FPGA Design On Third Order All Digital Phase-locked Loop Technology

In many fields of burst communication technology which is widely used, differential demodulation algorithm has good effect on Rayleigh fading resistance, but it is powerless when Rice Fading is more serious. On the contrary, coherent demodulation can effectively resist the effects of Rice fading. So the coherent demodulation method is widely used in modern communication.The research background of this paper is the burst communication technology. Firstly, the third order all digital phase-locked loop is designed to eliminate the influence of the frequency offset caused by the Doppler frequency shift and the propagation delay. Secondly, MATLAB simulation experiments and analysis of the system are carried. Finally, the FPGA design of all digital phase-locked loop is carried out. At the same time, the output of the phase-locked loop is put into the existing decoding module, which verifies the correctness of the design.The main contents and achievements of this dissertation are as follows:1. Firstly, this paper introduces the basic theoretical knowledge, including direct sequence spread spectrum, all digital phase-locked loop and the symbol timing estimation. Then the technology of all digital phase-locked loop is described in detail, including its basic structure and working principle. Finally, the algorithm of symbol timing estimation is studied, which lays the theoretical foundation for further research.2. In this paper, the Doppler frequency shift is existed in the burst communication system. The dynamic tracking performance of the PLL is analyzed, and the loop filter is designed for third order all digital phase-locked loop. At the same time, the performance curves of second order all digital phase-locked loop and third order all digital phase-locked loop are obtained. The results show that third order all digital phase-locked loop is better. Then the basic structure and error estimation algorithm of digital symbol timing synchronization loop are studied.3. Firstly, the simulation of third order all digital phase-locked loop for carrier synchronization system in different signal-to-noise ratio conditions are carried out. The results showed that to achieve the same frame error rate, third order all digital phase-locked loop coherent demodulation system improve the system signal-to-noise ratio performance than second order digital phase-locked loop. Secondly, the frame error rate curves are given with the change of the Doppler frequency shift acceleration.4. Finally, the FPGA design of third-order all digital phase-locked loop is completed. The simulation results are output to the existing decoding module to verify the correctness of the design.