Research And Implementation Of Synchronization Technique Of Digital Receiver Based On FPGA

FPGA (Field Programmable Gate Array) is a popular hardware platform, which provides the technology for realizing digital communication infrastructure. It is attractive in view of highly configurable performance, low power consumption and low cost. With the development of FPGA technique, it is capable of realizing the more complex and more configurable digital receiver. Among all the technique of digital receiver, synchronization is the most critical, and it is the basic part of digital receiver. So, this paper is mainly about the implementation of digital receivers' synchronization based on FPGA.This paper focuses on two synchronization algorithms: one is the Gardner symbol timing recovery algorithm, and the other is the Costas carrier synchronization algorithm. At first, we do research about two algorithms, and then analyse the details of implementation. After that, this paper proposes two implementation schemes based on FPGA: Gardner symbol timing recovery loop and the improved Costas carrier synchronization loop for QPSK. At last, the two schemes are realized partly by coding in Verilog HDL and partly by using Altera IP Core based on QuartusII 6.0 software enviroment.For verifying the feasibility of two schemes, testing methods of hardware and software are introduced respectively. Firstly, Gardner symbol recovery loop is tested by software method. Post placement and routing simulation is done by using ModelSim-SE6.2a and Debussy 5.3v9. Then we analyse the simulation results and draw the conclusion. Secondly, the Costas carrier recovery loop is tested by hardware method. The test is executed based on Altera CycloneII EP2C35F672C6 DE2 board and I.F.board which is designed by myself. From the hardware testing results, the scheme is proved to be applicable.