Design And Implementation On Algorithm Of Digitized Carrier Synchronization Loop

Synchronization plays an important role in communication systems. It is the precondition for the processing of information transportations. The performance of synchronization will directly influence the performance of communication systems. This thesis makes a deep research of digitized carrier synchronization technology and the algorithm's software implementation.The task of carrier synchronization is tracking the frequency and phase of a carrier wave, the most effective means for tracking small frequency deviation and the phase of a carrier is using the phase-locked loop (PLL). Therefore, first the paper investigates the fundamental theory of the phase-locked loop, in which we place stress on the phase-locked loop structure which is suitable for software implementation. Then the paper researches the operational principle and realization method of each subassembly of the digitized phase-locked loop, which includes numerical controlled oscillator, digital phase dectector, and digital filter etc., and also discusses the method of improving the performance of each subassembly. By comparing linear and digitized PLL's phase-transfer function, we obtained the relations between the two type PLL's parameters, thus gives out a scheme of digitized PLL's design. Then the paper introduces the operating principle of the digitized Costas loop used in spread spectrum communication systems. The algorithm of cross product automatic frequency control (CPAFC) and frequency bin technology is used for tracking larger frequency deviation. The paper gives out a scheme of digitized carrier synchronization loop, in which the digitized Costas loop is used as a basic part while CPAFC and frequency bin technology as auxiliary. Then we validate the algorithm's correctness by establishing a dynamic simulation model of the loop, in which we obtained some experiential values of certain parameters. Based on the earlier work, we implemented the algorithm by digital signal processor (DSP), which makes a further validate of the algorithm.Finally, the paper gives out a scheme of digitized carrier synchronization loop for software defined radio receiver which is based on the hardware platform composed of FPGA and DSP.