High-speed ADC Interface Design Based On JESD204C

With the rapid development of computer and communication technology,high-tech industries such as 5G,Internet of Things,and autonomous driving have gradually melted in our daily lives.Demands for data transmission speed are continuously increasing,causing the industry to increase the speed of data transmission interfaces.The traditional parallel transmission interface can afford high sample rate and sample speed,but it has the disadvantages of too many pins,increased wiring difficulty,increased cost,serious electromagnetic interference and crosstalk,etc.Therefore,high-speed serial interfaces have become a commonly used high-speed data transmission interface.This thesis implements transport layer and link layer of a high-speed ADC interface based on the JESD204 C protocol.Compared with the previous version JESD204 B,the maximum channel rate of the JESD204 C interface has been increased from 12.5 Gbps to 32 Gbps,and new features such as 64b/66 b and 64b/80 b encoding,FEC encoding and decoding,and synchronization head stream have been added to further improve link efficiency and stability.This thesis analyzes the key features and addresses the technical problems of JESD204 C,such as the data mapping methods,encoding/decoding algorithms,link synchronization and other technical difficulties.In this thesis,the hardware implementation method of these algorithms is investigated and realized using the EDA tools such as VCS and Verdi to complete the RTL coding,behavioral simulation,and error statistics of the transport layer and link layer of the JESD204 C interface.The JESD204 C interface are verified on the Artix-7series FPGA Nexys video using two methods: Micro Blaze combined with JESD204 C and XADC combined with JESD204 C.The JESD204 C interface designed in this thesis supports up to 16 channels of 16-bit ADCs simultaneously working in single-channel mode or multi-channel mode.The probability of the CRC function not detecting a 3-bit error is lower than 0.004%,and the FEC function can correct up to 9 consecutive error bits in each 2048 bits of data.JESD204C will become the commonly used high-speed serial interface protocol in the next few years,but domestic scholars' research on JESD204 C is still in its infancy.Hence,the research and realization on the protocol is of comparative value in both theoretical research and actual practice.