Design And Implementation Of High-speed Memory Data Transmission Interface Based On FPGA

With the development of electronic information technology at home and abroad,the era of big data has arrived.Collision in the field of electronic information countermeasures has become the main means of collision in the military field of all countries in the world.Many new and complex radars and waveforms continue to emerge,making electronic countermeasures change.It is more complex and diversified.Therefore,the acquisition and processing of intelligence in electronic information warfare is facing huge difficulties.The booming development of artificial intelligence technology provides a good way to solve this problem.What comes with it is the explosion of intelligence data.Due to the growing demand for data processing and massive data processing,seeking a data processing system with high-speed storage and high-real-time processing functions is a prerequisite for the intelligent realization of electronic information countermeasures.This paper studies and designs a high-speed memory based on the requirements of the radar radiator intelligent recognition project for this high-speed,large-capacity,and high-real-time data processing platform.On the basis of disk array technology and high-speed interconnection system,complete the design of high-speed storage system,system highspeed interconnection architecture and high-speed data transmission interface selection,design and implementation according to the functional requirements of high-speed memory.The main work of this paper is as follows:1.Completed the demand analysis for the transmission interface of the high-speed storage system.According to the project's requirement for the radar intermediate frequency data acquisition rate of 20Gbps in the system,the demand analysis of the internal high-speed data transmission interface of the high-speed memory system was completed.The transmission rate of the inter-board communication interface is 20Gbps and the transmission bandwidth is 2GB/s.Data recording and return visits The transmission bandwidth of the interface is up to 2GB/s.2.Selection of high-speed interconnection architecture and high-speed interface.According to the needs of the project,through the research and analysis of different high-speed interconnection architectures and high-speed bus interfaces,the VPX bus architecture,SRIO high-speed bus and PCIE high-speed bus are finally selected for research.The VPX bus is used as the high-speed interconnection architecture of the system.SRIO bus and PCIE bus are used as system high-speed data transmission interfaces.3.Complete the overall design of the high-speed storage system and the design and selection of hardware circuits.According to the characteristics of the selected VPX bus architecture,SRIO high-speed bus and PCIE high-speed bus,the overall framework of the high-speed memory system based on the VPX bus architecture and the design of internal functional blocks are completed.The main content of this article is to complete the design and implementation of the SRIO and PCIE high-speed transmission interface in the system.4.Design and implementation of SRIO interface.First,research and analyze the SRIO bus protocol.On this basis,complete the design,implementation and simulation of the interboard SRIO interface.Second,complete the construction of the test system,including the optical fiber module of the data exchange board,the DDR3 module and the internal data storage board.The realization of the SATA3.0 storage array finally completed the test of the SRIO interface between the entire system board,with a test rate of 20Gbps and a bandwidth of 2.0GB/s.5.Design and implementation of PCIE3.0 interface.First,the protocol and communication mode of the PCIE3.0 bus are researched and analyzed.On this basis,the design of the PCIE3.0 interface and the realization of the XDMA communication module are completed.Secondly,the entire test system of the data exchange board and the data storage board is completed.Finally,through the development of the PCIE3.0 interface driver,the test of the data transmission and rate of the data recording and playback interface was completed.The final test bandwidth ranged from 1.9GB/s to 2.0GB/s,and the interface rate range was 15.2GT Between/s?16.0GT/s,it completely matches the bandwidth of the SRIO transmission interface between the entire system board.Through the design of high-speed memory SRIO and PCIE3.0 transmission interface based on the VPX interconnect architecture,this paper makes the SRIO transmission interface rate between the entire system board reach 20Gbps,the transmission bandwidth reaches 2GB/s,and the transmission bandwidth of the PCIE3.0 interface reaches 1.9GB/s?2.0GB/s,the transmission rate of the interface reaches 15.2GT/s?16.0GT/s,which meets the index requirements of the radar radiation source intelligent identification platform for the data transmission interface of the high-speed storage system.