Logic Implementation Of High-speed Inter-board Interface Based On FPGA

Multibeam bathymetric system is a device that can be carried out efficiently detection of the seabed topography, with the promote of time, multi-beam bathymetric sonar products are constantly upgrading as time progresses, now is widely used in various fields such sa ocean engineering measurement, seabed resources exploration, surveys of the marine environment and undersea target detection, etc. it has now become one of the essential detection equipment in ocean exploration. However, when multi-beam bathymetric system equipment obtain excellent performance, it also brings a lot of real-time data transmission and processing at the same time and they need complete quickly, the transmission performance give the system a high demands. This paper mainly focuses on solving the high-speed data transmission problem in multibeam bathymetric system. As the transmission speed of traditional protocol couldn't reach the demand, high-speed data transfer protocol is imperative.First, the paper did research on all kinds of high-speed transmission trunk. And then the paper introduced RapidIO high-speed transmission protocol in order to solve high-speed data transmission problems in multi-beam sounding system. The paper built a high-speed data transmission system based on RapidIO protocol, and composed by Cyclone IV FPGA processing platform and RapidIO network switching platform based on Tsi578. Besides, the paper made a detailed description of RapidIO system's network topology,RapidIO protocol's layered structure, each layer composition and function, and also I/O work standards' several basic operation& formats in logical layer. Afterwards, the paper discussed approaches we used,involving introducing Altera's SRIO IPcore and also researching Cyslone IV's high-speed transceiver.Secondly, the hardware design of the entire high-speed data transmission systems were demonstrated, and introduce the design of hardware circuit's every module, including power module, clock module, interface module and configure module. Because the circuit of this thesis involved a high-speed circuits, so it's a high-speed circuit design, for the layout strategy of the circuit, the differential traces, stack design and the impedance matching, the paper coplete the corresponding analysis, demonstration and simulation .Then the article design the RapidIO hardware systems and software system in SOPC platform, simulate the applications of the RapidIO system, and get the simulation results;Finally, based on the completion of the circuit design of high-speed data transmission system ,comlete the debugging of the transmission system. This design use Verilog HDL language and IP core modular in the Quartus ? software environment complete the FPGA control logic for data transmission, complete the network transmission functional test ,proposed the measure method of the transfer rate and obtained the test results.