The Research And Design Of SPI Interface Circuit In High Speed ADC

High-speed ADC has been widely used, in the radar, wireless communications,high-speed data acquisition and other fields. As the core module for data sampling and conversion, the data transmission between ADC and external controller,and its performance improvement, have become the hotspot of chip developers. SPI interface bus has been widely used in data communication because of its fast transmission speed, low signal line occupation, high signal transmission accuracy and full duplex.Therefore, the design concept of integrating SPI interface in the high-speed ADC chip has become the new trend in the current high-speed ADC field.Based on the architecture of a high-speed folded and interpolated ADC , this thesis studied and designed the SPI interface circuit applied to high-speed ADC, achieving the serial data communication between high-speed ADC and external controller. The thesis also studies the multi-functional configuration of high-speed ADC, including calibration enable, data clock DCLK phase selection, multi-channel power-off control,coding test function. The SPI interface configuration on the ADC has saved the number of chip pins, therefore greatly reducing the chip area. In addition, the thesis studied the calibration on the mismatch error of the high-speed ADC through the SPI interface circuit, including the misregistration of the sample-and-hold circuit and the sampling time mismatch of the timing generation circuit. This manual calibration method has not only high calibration accuracy, but also better flexibility and controllability.This thesis uses the Verlilog HDL hardware description language to complete the RTL design of the SPI interface circuit. The function and its correctness of the SPI interface circuit has been simulated and verified by Modelsim simulation software. In the digital-analog hybrid platform CadenceAMS, The SPI interface circuit of RTL level and the error calibration circuit based on TSMC 0.18?m CMOS process are simulated. The result shows that the error calibration can be fulfilled by SPI interface circuit. The ENOB of sample and hold circuit is increased from 8.93bits to 11.03bits,The calibration time of the circuit is 0.09ps, which reduces the circuit mismatch error and improves the circuit performance, thus improving the overall performance of the high-speed ADC. Then, the thesis deals with the design of the SPI interface circuit FPGA hardware implementation and verification. Finally, based on the TSMC 0.18?m CMOS process library, the SPI interface circuit is implemented and verified by ASIC,and the integrated circuit is synthesized by using the Design Compiler synthesis tool.The results show that the SPI interface circuit timing meets the design requirements.Finally, the integrated circuit has been simulated and verified, and the thesis uses the IC Compiler tool to achieve the automatic layout and wiring of SPI interface circuit and completes the layout design.