Design And Implementation Of High-speed Interactive Interface Between FPGA And DDR Memory

With the rapid development of integrated circuit technology,the speed of processing data has been continuously improved.FPGA has a wide range of applications in many fields due to its high flexibility and abundant resources.With DDR SDRAM as an external memory,it has the advantages of fast transmission speed and large capacity,and has extensive research significance in high-speed data transmission system.The FPGA chip has the characteristics of comprehensive functions and user configurability.Due to the large area and limited clock signal frequency,the continuous increase in frequency will cause a large phase difference between the internal clock phases of the chip.Therefore,the internal frequency of the FPGA usually does not exceed 200 MHz.The I/O logic unit(IOL)in the FPGA is an input-output logic interface,which is used to process data read and written to external devices inside the FPGA.DDR memory is divided into first generation DDR,second-generation DDR2,and third-generation DDR3.Each clock can read/write data at 2,4,and 8 times the speed of an external bus,and can run at 2,4,8 times the speed of the internal control bus.This thesis studies the interaction of data,clock,and control signals with FPGA when SDRAM,DDR/DDR2/DDR3 are external memory,among which the IOL module processes the signals.The interface realizes receiving external high-speed signals to reduce speed processing,configurable gearing 1:2,1:4,1:8,1:10,1:7,and sending FPGA low-speed signal increase speed processing,configurable gearing 2:1,4:1,8:1,10:1,7:1,signal delay processing and corresponding flags are generated.The data and clock can be configured as center or edge sampling.The data transmission adopts double edge sampling,and the command address signal adopts single edge sampling.Memory DDR data and clock continuity are achieved by changing the clock domain through the FIFO.The whole is divided into two parts:designing the circuit and verifying the test.The design uses a top-down design method and a modular design idea.Including input module,output module,data delay module.Circuit adopts full custom design method;the virtuoso software is used to draw the circuit diagram and simulate the inspection.The verification uses VCS compiler to simulate the simulation environment,build a testbench,add Verilog files to generate test incentives and expected results.It can be verified that the function of the circuit is correct,and the mode of the circuit under different configurations can be realized.HSPICE simulates the performance of the circuit to ensure that the timing achieves the design goals in different modes,and continuously improves the circuit until the design meets the requirements.So as to realize the design of high-speed interactive interface.The innovation of the design is to increase the circuit function.The design adds the FIFO clock domain conversion module to continue the discontinuous signals and increase the time margin between the two stages of registers,which can improve the accuracy of data transmission in high-speed mode.The design is based on the UMC28nm process,reducing the chip area and improving integration.there are 392 interfaces around the chip,and each IO interface supports different modes.After verification by different simulation process corners,the circuit realizes the design functions and meets the change of the FPGA configuration and selecting signals can be compatible with different external memories.Circuit design can achieve read and write operation speeds up to 533MHz(DDR1)800MHz(DDR2)1066MHz(DDR3),and supports up to 32-bit computing.The voltage is 1V(±5%),the total design chip capacity is 46K.The area of a single IO interface is 70x41.6um~2,and the average value of the dynamic power consumption maximum mode measurement is 300u W under the typical corner.Based on the accurate transmission of signals,the processing speed and width are continuously improved,the functions of the FPGA are updated and improved,and the applicable scope of the FPGA is expanded.