Research And Design Of DTC In Fractional SSPLL

With the rapid development of wireless communication technology and the continuous improvement of data traffic,higher performance is required for the frequency synthesizer.Therefore,in recent years,new-type high performance phase-locked loops such as SSPLL,ADPLL,BBPLL,and SPLL have become the research hotspot,and the application of DTC to new-type phase-locked loops makes it exhibit better performance.This thesis will research the key technology of DTCbased fractional SSPLL,which focuses on the design of the DTC architecture and DTC gain calibration.The main work of the thesis is to design a DTC circuit structure applied to SSPLL.Starting from the phase-locked loop,the thesis introduces the principles of the traditional charge pump phase-locked loop and the fractional phase-locked loop,and analyzes the noise of the two structures separately,and introduces the principle of the △Σ modulator in the fractional phase-locked loop,and summarizes the suppression technology of quantization noise.After analyzing the working principle of the fractional SSPLL based on DTC,a suitable DTC circuit structure was selected for design work,the circuit layout was given,and the post-simulation was completed.Another work of the thesis is the gain calibration of DTC.The thesis first summarizes the principle of digital predistortion technology applied in calibration,introduces the least square method and optimization algorithm,gives a model of DTC calibration,and carries out modeling and loop simulation on Simulink platform.The DTC circuit structure is designed based on 65 nm RF CMOS process.The layout area is0.11mm×0.07 mm.In the worst case,the errors of DNL and INL are 1.8LSB and 4.4LSB respectively.The shortest delay interval is 120 fs and the longest is 330 fs.The total delay time is0.27 ns,which covers approximately 9 VCO periods.