The Key Research Of Low-Noise Frequency Synthesizer

As a key module of wireless and wired communication,the frequency synthesizer provides local oscillator signals and performs frequency modulation.Aiming at the design goals of low phase noise,low spurious,the research of this work focuses on the phase noise generation mechanism,two-point modulation calibration technique,low spur and phase noise design technology,and quantization noise suppression technology.First of all,the frequency synthesizer is briefly discussed.The existing frequency synthesizer architectures and their advantages and disadvantages are dicussed for comparision.The S-domain transfer function model of the charge pump phase-locked loop(CPPLL)and the Z-domain transfer function model of the all-digital phase-locked loop(ADPLL)are derived.Then,the design specifications of the bluetooth frequency synthesizer are presented.Secondly,aiming at the oscillator phase noise problem in the frequency synthesizer,an in-depth study of the existing phase noise generation mechanism and theoretical models is carried out.An accurate phase noise analysis model based on impulse sensitive function(ISF)is proposed,which can simultaneously quantify the influence of transistor flicker noise and thermal noise.Based on the proposed analysis model,the phase noise prediction of different oscillator structures using source damping resistors is carried out.The error between the model prediction value and the simulated value in both 1/f ~2 and 1/f ~3 area is less than 1 d B,providing an effective analysis tool for phase noise optimization of various oscillators.Thirdly,aiming at the modulation rate and bandwidth bottlenecks faced in the polar modulation transmitter,the existing two-point modulation scheme and its transfer function are discussed.A fast two-point modulation gain/delay calibration scheme is proposed,which can complete the delay and gain calibration within 15μs respectively.A polarity detector and a duty cycle detector are used to track the gain/delay mismatch information of the two modulation paths.By using a digital-to-time converter(DTC),the mismatch is compensated.When the normal calibration process is completed,the loop up table stores the calibration value,further shortening the calibration time to 62.5 ns.A Class-C voltage-controlled oscillator,combined with capacitance desensitization technology and cross bias technology to improve linearity and reduce phase noise.Finally,the proposed CPPLL is implemented in a HHGRACE 110 nm CMOS technology,occupying 2.7 mm~2 area.The simulated and measured results show the proposed CPPLL can complete the calibration within 30μs.The measured phase noise is-76.7 d Bc/Hz@100 k Hz,-110.2 d Bc/Hz@1 MHz.The CPPLL achieves a rms jitter(Root Mean Square Jitter)of 6.2 ps,corresponding to a-211 d B Fo M(Figure of Merit).Then,aiming at the quantization noise problem faced by the ADPLL,the quantization noise generation of the key module time-to-digital converter(TDC)is analyszd.A low-noise ADPLL architecture based on multi-delay line TDC(MDL TDC)is proposed.A high-precision path selection MDL TDC,combined with TDC offset calibration,is proposed to achieve an effective 4 ps resolution and 24 d B TDC quantization noise suppression.The true fractional divider consist of isolated constant slope DTC and the multi-mode frequency divider is used to eliminate the quantization noise.By using the gain calibration,the fractional spurs introduced by the DTC gain mismatch are reduced.The ADPLL prototype is taped-out in SMIC 40 nm CMOS process,occupying a chip area of 0.36 mm~2.The measured results show that through TDC offset and DTC gain calibration,the fractional spur and phase noise of ADPLL are suppressed by 25 d B and 22 d B respectively.The ADPLL realizes a 0.78 ps rms jitter,corresponding to a-235 d B Fo M.Finally,aiming at the problems of loop spurs and phase noise caused by nonlinear circuit modules in ADPLL,a low-noise spur immune ADPLL architecture is proposed.By using a configurable PDS DSM,the spur caused by phase noise can be removed.Moreover,a configurable phase interpolator with 0.125/0.25/0.5/1.0 division step is used to decrease frequency division step,leading to an 18 d B quantization noise suppression.A prototype using the aforementioned techniques was designed in a SMIC 40 nm standard CMOS process,occupying a 0.99 mm~2 silicon area.The post-layout simulated results show,with PDS turned on and off,the fractional spur is-59 d Bc and-20 d Bc,respectively.By reducing the frequency division step from 1.0 to 0.125,18 d B quantization noise and 6 d B phase noise suppression are achieved,respectively realizing a 4.218 ps rms jitter,corresponding to a-220.5 d B Fo M.The work of this thesis gradually deepens from system architecture design,circuit optimization,and key noise suppression technology implementation,providing theoretical basis and design reference for the design of low-noise frequency synthesizers.