Design Of Key Modules Of CMOS Readout Circuit In Terahertz Signal Detector At Normal Temperature

Terahertz technology has developed very rapidly in recent years.Terahertz signal detection and imaging technology has always been a hot and complex frontier subject.In the detection of terahertz signals,the basic function of the readout circuit is to convert the signal intensity irradiated by the light wave into a voltage or current signal,read and digitize it.Good readout circuit performance determines the accuracy of signal detection.This thsis is based on the characteristics of the Nb₅N₆ microbolometer,using0.18?m CMOS process,designed for the back-end circuit part of the readout circuit array of the terahertz signal detector,the array size is 8×8 as the target.The research group has done many designs in the pixel level circuit module of the readout circuit,but the output is the amount of analog voltage.In this thesis,the analog voltage output by the design circuit is processed.The circuit includes a switched capacitor(SC)amplifier,successive approximation analog-to-digital converter(SAR ADC),the system's readout timing circuit and parallel-serial conversion circuit.The SC amplifier can effectively suppress the channel resistance thermal(KTC)noise and fixed pattern noise in the front-end analog circuit,and amplify the discrete-time signal to provide a stable DC level for the SAR ADC.In order to provide a reference voltage to work with SC amplifiers,the thesis designed a bandgap reference circuit that is not affected by temperature.The high-gain op amp in this bandgap reference uses a two-stage cascade structure to improve gain and output swing;in order to accurately digitize for analog signals,the thesis designs an analog-to-digital converter with a resolution of10 bits,and the effective number of bits for system simulation reaches 9.36 bits.At the end of the thesis,a read-out sequential circuit is designed to control the orderly work of each module,and a parallel-serial conversion circuit is used to convert 10-bit parallel digital signals into serial output to reduce the number of pads on the readout circuit array chip.The readout circuit array is formed by cascading the last row of each column of the readout circuit array,and a series of 10-bit digital conversion results are generated every cycle by way of row-by-row readout.The post-simulation was carried out under the condition of TT process corner.The simulation results show that the expected design requirements are met,and the precision is very high,which is suitable for larger arrays.