Design Of Hall Sensor Readout Circuit

With the constant innovation and development of electronic technology,Hall sensors as signal sensing elements are widely used in automobiles,mobile phones and automatic control and other aspects,And it is moving toward the trend of intelligence,miniaturization,high sensitivity,and high integration.Therefore,the research of the Hall sensor readout circuit is very important.The noise suppression and integrated design are two key points of the Hall sensor readout circuit.The paper studies the integration of Hall sensor readout circuits,focusing on the research of noise suppression,including the following specific content:Firstly,based on MATLAB,the whole structure of the Hall sensor readout circuit is modeled and simulated.The influence of non-ideal factors on the actual circuit is mainly considered,and the design parameter range is determined.The second is to use a chopper circuit structure based on high-frequency modulation,using the principle of modulation and demodulation to reduce the low-frequency noise and offset problems in the circuit design to achieve low noise requirements.The third is to use a variable-gain operational amplifier structure to adapt to changes in the output signal of the front-end Hall sensor to achieve accurate signal processing within a certain range.The fourth is to use a second-order sigma-delta modulator with low-frequency noise suppression to reduce the error caused by analog component matching on the signal conversion accuracy and complete the conversion of analog signals to digital signals.Finally,the overall circuit is designed and the layout and post-simulation are completed.The characteristics and innovations of this paper are as follows:On the one hand,the use of capacitance multiplexing technology to reduce the layout area,That is,in the circuit,the gain and feedback factors are realized by using the ratio of the same sampling capacitor and the integral capacitor,and the matching of the circuit is improved and the circuit performance is improved while reducing the use of the capacitor.On the other hand,chopper technology based on high frequency modulation is used to reduce low frequency noise and offset in the circuit.Because the signals in the front-end variable-gain op amps and the first-order integrators are vulnerable to low-frequency noise,chopping structures are added to the design to improve the accuracy of data conversion.Based on the SMIC 0.18?m mixed-signal CMOS process,the overall structure and layout are completed.After simulation verification,under the conditions of 437.5Hz signal frequency,256KHz clock frequency,and 3.3V power supply voltage,The signal-to-noise ratio(SNR)of the circuit is 83.03dB,the effective number of bits(ENOB)is 13.5bits,the layout area of the entire circuit is 1.05mm×0.73mm,and the power consumption is 2.1mW,which meets the application requirements.