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Design Of Low Temperature SNSP Readout Circuit

Posted on:2019-04-21Degree:MasterType:Thesis
Country:ChinaCandidate:Y P DengFull Text:PDF
GTID:2428330590975459Subject:Engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of quantum information technology,the traditional single-photo detection technology is gradually replaced by nanowire single-photo detection technology based on superconducting thin film materials due to the disadvantages of large detector noise,low detection efficiency and complicated external control circuit.Therefore,the corresponding readout circuit design has also gradually become a hot issue in integrated circuit research.In the system studied in this thesis,the detector needs to work at a temperature of 2.5K.In order to reduce the transmission line effect and avoid the impedance mismatch between the coaxial lines,the corresponding readout circuit must amplify and sample in a 4.2K environment,then transmit the detected signal through a path to a room temperature FPGA in the processing.The key consideration readout circuit design can work in the environment 4.2K.First of all,to complete thetest work of devicesat low temperature,according to the device's low temperature characteristics and-40?~27? temperature range of the simulation results,estimated circuit performance changesunder 4.2K.Second,the use of bias structure adjustable design method to ensure the normal operation of the circuit.In this thesis,the low temperature sensing circuit based on superconducting nanowire single-photon(SNSP)is designed by using TSMC 0.18?m CMOS technology,including the key modules of amplifier,comparator and multiplexer(6:1).Amplifier with single-turn double structure,differential structure for signal processing;use feedback,capacitance and other ways to extend the bandwidth.Comparator designed by using cross-coupling to obtain a relatively high gain can be determined if the signal is determined.The multiplexer will be six low-speed parallel data into high-speed data output.In the layout design,the use of deep N-well and other techniques to reduce noise coupling interference.The array chip area is 1.11 mm × 1.41 mm.The simulation results show that the low-temperature amplifier achieves a gain of 20 dB and a bandwidth of 140 kHz ~ 1GHz by increasing the bias current at-40?.The comparator can determine whether the signal is available or not.Multiplexer chip area is 1.10 mm × 0.38 mm,to achieve parallel conversion,the 100 Mbps six-way data into 600 Mbps all the way to the data output.
Keywords/Search Tags:Readout circuit, Cryogenic amplifier, Single to double circuit, Comparator, Multiplexer
PDF Full Text Request
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