Design Of Infrared Sensing Readout Circuit Based On Array Time To Digital Converter

As one of the key technologies of three-dimensional imaging applications,the infrared readout integrated circuit(ROIC)can accurately measure the photon flight time and obtain a variety of useful information.Potential applications for photon timing ranging imaging systems include advanced interceptor seekers,target recognition,navigation of autonomous robots and vehicles,obstacle detection and topography.However,with the expansion of the array size,not only the system's accuracy,linearity,dynamic range and other performance are increasingly difficult to improve,but also serious power consumption,noise,crosstalk and other issues will appear,which severely limit the application of large array ROIC systems.Aiming at the application background of laser ranging and 3D imaging,this paper proposes a brand-new array TDC-type ROIC to achieve active three-dimensional imaging of the target.Firstly,not only in order to meet the requirements of design specifications,but also considering some factors,such as power consumption,cost,and timing control,this paper selects a clock-driven ROIC architecture,and on this basis designs a two-stage local shared time-to-digital conversion circuit(TDC).The high-segment is an 11-bit periodic counting TDC for exclusive use of pixels,which realizes coarse counting of the time interval.The low-segment is a 1-bit phase fine resolution TDC shared by pixels,which realizes fine counting of the time interval,thereby realizing the measurement range and resolution at the same time and meeting the application requirements of high precision and wide range.Secondly,by optimizing the circuit logic,the dynamic phase sampling of single-pixel TDC circuit transforms from DFF to DFF+TG mode.By freezing and then sampling the dynamic phase information,the probability of occurrence of error between segments is greatly reduced.Last but not least,the layout physical design emphasizes the suppresson of parasitic effects on the premise of a compact area,and improve the delay matching of critical paths,such as the selection of a suitable power supply network.The externally introduced power /ground lines are placed on both sides of the layout,and power is supplied to the pixels from both ends of the array at the same time,which suppresses the drop of the power supply voltage and improves the stability of the ROIC chip.Fabricated in TSMC 0.18?m standard CMOS process,the Cadence EDA tools is adopted to complete the construction of the ROIC system,layout design,pre-simulation,post-simulation and tapeout verification.Under the 1.8/5V power supply voltage,500 MHz high-frequency count clock,50 MHz low-frequency transmission clock,20 kHz frame frequency and room temperature 27 °C conditions,The test results show that the designed ROICsystem has 1ns time resolution,4?s test range,-0.15LSB~0.15 LSB differential nonlinear DNL,-0.3LSB~0.32 LSB integral nonlinear INL,and approximately 490 mW power consumption,basically satisfying the design The requirements of the indicator.Finally,a 3D imaging experiment is performed using a 3Dimaging receiver to obtain the intensity and distance information,and 3D imaging of the measured object is achieved.