Theoretical Analysis Study And Design Of The 9 Bit SAR ADC Based On Multi-bit Conversion

Successive Approximation Register(SAR)ADCs are mainly composed of digital circuits,with only a small amount of analog circuits,which have significant advantages in terms of size and power consumption,and have always been favored by the market and academia.However,due to the limitations of its serial conversion method,SAR ADCs are usually only suitable for applications with medium resolution and slower speeds.Therefore,to fully utilize the high energy efficiency of SAR ADCs,an improved architecture is needed to apply it to high-speed fields,making it a research hotspot in the field of ADCs.To meet the needs of high-speed communication systems,this paper designs a 9-bit500MS/s asynchronous timing Flash+SAR hybrid architecture ADC.The ADC uses a 2-bit/cycle data conversion method and uses three comparators that work simultaneously,which doubles the quantization speed compared to traditional SAR ADCs.To address the non-linear error introduced by the mismatch of the three comparators in the Flash+SAR hybrid architecture ADC,this paper proposes a novel method for dynamically calibrating the comparator mismatch voltage.The method obtains the mismatch information from the result of the last conversion phase and performs consistent calibration of the mismatch voltage of the three comparators in the background,without occupying any additional conversion phase,reducing the impact of comparator calibration on ADC quantization speed.Additionally,to better withstand PVT variations in asynchronous timing high-speed ADCs,this paper proposes a method for dynamically adjusting the ADC conversion speed-power.The ADC designed in this paper was implemented with 40 nm CMOS technology for overall layout design and front and back simulation verification.The results show that when the ADC’s power supply voltage is 1.1V,the sampling rate is 500MS/s,and the input signal frequency is close to the Nyquist frequency of 250 MHz,the overall power consumption of the system is only 2.11 m W,the signal-to-noise distortion ratio is 54.9d B,and the effective number of bits is 8.8bit,and the spurious-free dynamic range reaches 68.3d B.Meanwhile,the ADC’s static performance is good with DNL and INL both less than 0.5LSB.