14 Bits 200MSPS Self-calibration Current-Steering DAC Design

Digital to analog converter (DAC) is regarded as the transform device between digital and analog system, and It is self-evident that DAC is important in electronics system. Due to its characteristics of high-speed, high-resolution and small area consumption, segmented current-steering structure is adopted by many DAC designers. However it is still difficult to design a current-steering DAC with the resolution of 14bits. With the development of scientific technology, the requirement of high resolution DAC is becoming more and more urgent. So calibration approach is introduced to improve the dynamic performance in high resolution digital to analog converter (DAC)In this paper it proposed a self-calibration current steering DAC based on 1P6M SMIC0.18 standard process, the main work of it is as follows:(1) In order to get low power and small area consumption, it employs segmented current-steering structure.(2) Arming to reduce the amplitude of the switch control signal, intersection and the influence of clock feed through the overall performance, a switch driving circuit is adopted in this design.(3) The digital self-calibration method is introduced in this paper to improve the SFDR, it selects the five high significant current source by random way and transforms the mismatch factor of each current source into white noise,.(4) Implementation the proposal calibration method and the whole DAC with the EDA tools such as DC and ICC.The method of calibration is implemented by Verilog, verified by Modelism and Cadence-AMS. The verified simulation result based on SMIC 0.18 shows that at 1.8V supply,and 1 MHz frequency, sampling frequency 200 MHz sampling frequency, DAC achieves a SFDR of 92dB with a load resistance of 25 ohm and a load capacitance of 4 pF, the SFDR is 92dB and the dynamic of QAC has greatly improved compared with the un-calibration DAC.