SRAM In-memory Computation Mode Based On Balanced Pre-charging And Group Decoding

Current computing systems based on the von-Neumann architecture are limited by memory,power consumption,and bandwidth.People try to develop new architectural methods to avoid these limitations.Among them,in-memory calculations are widely studied because they can process data in the array,reduce the requirements for memory bandwidth,and thereby save energy.It can be found by reading the literature that the current SRAM in-memory calculation usually adopts two reading methods.The first is multi-row reading,which has the advantage of high parallelism.However,the use of analog calculation may cause errors in the data read,which is difficult to meet some applications that require high accuracy.The other method is single-row reading,which is a digital calculation and is more accurate.Because it is a single-row operation,for some applications with a large amount of data,it requires many cycles,and it is difficult to meet the requirements for operating speed.In this paper,a compromise is made between these two reading methods,and a balanced pre-charge and group decoding method is adopted to design a SRAM in memory calculation method that realizes one-time pre-charge and continuous reading.This design makes full use of the balance transistors in the existing pre-charge circuit,without adding any additional transistors,the bit line voltage after reading can be rebalanced and used for the next reading,realizing a pre-charge and continuous reading function.At the same time,a group decoding strategy adapted to the balanced pre-charge path is proposed,which realizes the optimization of the global reading speed and reading accuracy of the existing reading method.Compared with the analog in-memory calculation and reading method of multi-row parallel reading,the calculation accuracy is improved;compared with the single-row memory calculation and reading method,this design improves the overall calculation speed.The design improves the overall calculation speed.Based on 65 nm technology,this paper simulates the proposed structure on the basis of an ordinary 6T storage array.The simulation results show that the read static noise tolerance can be improved by up to 13.8% in the continuous read mode.Combined with the group decoding method,the global read speed can be increased by 75%.And it can reduce the power consumption of continuous reading by up to 11.58%.In addition,it can also be widely used in various storage structures.This method has been applied to the existing inmemory computing structure,and its effectiveness has been verified.