Research On Key Techniques Of Processing-in-Memory Chip Design

In recent years,with the rapid advancement in the fields of computational science and information technology,along with the emergence of big data,artificial intelligence,and deep learning,the demand for high-performance computing platforms has grown significantly.While computer performance has been continuously improving with the progress in semiconductor technology,the speed gap between memory and processors has been widening,resulting in data transfer becoming a bottleneck for performance,commonly referred to as the von Neumann bottleneck.To overcome the limitations of the von Neumann bottleneck,the concept of ”processing-in-memory” has been proposed.The core idea of processing-in-memory is to integrate computing functions with data storage,allowing computations to be performed directly within the memory,significantly reducing the need for data transfers and alleviating the burden on memory bandwidth,thus greatly improving computational efficiency.Based on this,processing-in-memory offers new possibilities for applications such as neural network computations,medical image processing,and the Internet of Things(Io T)for large-scale data processing.Despite rapid development since its inception,current processing-in-memory chips still face several challenges,including limitations in storage capacity,issues related to stability and reliability,and energy consumption.As processing-in-memory is still in its infancy,this dissertation aims to explore new applications based on processing-in-memory,investigate novel processing-in-memory architectures,and achieve higher performance and more versatile processing-in-memory technology.This dissertation combines key technologies of processing-in-memory chips to conduct research on three essential aspects: the novel pricessing-in-memory architecture,the innovative processing in-memory training methods and the novel processing-in-memory medium.The main work includes three key aspects:1.In order to investigate the novel processing-in-memory architectures,the dissertation introduced a novel reservoir computing architecture based on processing-in-memory.It explored the hardware architecture and mapping techniques required for implementing reservoir computing.In addition,the dissertation delved into the development of efficient input encoding and nonlinear transformation circuits,a reconfigurable reservoir computing layer with randomly connected neurons,and a reservoir node current conversion module.The dissertation also presented a reservoir computing architecture that integrated with SRAM-based processing-in-memory and established a comprehensive software and hardware platform to enable complete reservoir computing.The functionality of the reservoir processing-in-memory chip was validated by implementing NARMA10 time series and continuous speech recognition tasks on the proposed software and hardware platform.When compared to conventional reservoir computing architectures built using pure digital circuits,the proposed reservoir processing-in-memory hardware architecture offered significant advantages.In comparison to the reservoir computing architecture built on conventional digital platforms,the energy consumption of the reservoir computing architecture implemented with an all-digital circuit is 1.55 times that of the proposed reservoir computing architecture based on processing-in-memory.Additionally,the required number of operations is 2.08 times higher than the proposed processing-in-memory reservoir computing architecture.2.To explore the novel processing-in-memory training methods,the dissertation introduced an architecture for spiking neural networks based on processing-in-memory with on-chip unsupervised learning.The research delved into a hardware-friendly spiking neural network model based on an processing-in-memory architecture.The design included a 9T1 C SRAM processing-in-memory unit based on charge sharing,a Reconfigurable Multi-bit PIM Multiply-Accumulate(RMPMA)module,a Programmable Highprecision PIM Threshold Generator(PHPTG),and a rail-to-rail input dynamic comparator with low static power consumption.A low-area overhead,low-energy on-chip SpikeTime-Dependent Plasticity(STDP)hardware and algorithm were designed based on this processing-in-memory architecture.The introduction of the proposed winner-take-all mechanism significantly reduced the number of weights in the lateral inhibition layer.In comparison to other research endeavors,this design achieved an accuracy rate of 92.1% in recognizing the MNIST handwritten dataset,with an energy consumption of 0.47 n J per pixel learned.This work represented a significant contribution in the field of on-chip unsupervised learning and processing-in-memory,demonstrating substantial gains in energy efficiency and recognition accuracy for the MNIST dataset.3.To investigate the novel processing-in-memory medium,the dissertation proposed an processing-in-memory logic computing architecture with independently programmable row and column directions,integrated with memristors within a non-volatile SRAM.The design included an 8T4 R non-volatile SRAM cell structure with multiple operational modes and a sensitive amplifier with dual-mode single power supply.Based on this foundation,the dissertation explored the implementation methods of the architecture in regular SRAM mode,non-volatile SRAM mode,programmable in-memory logic computing mode,and binary content-addressable memory mode.The research also investigated three mapping methods for logic computations within the programmable in-memory logic computing mode.When implementing a 1-bit full adder,only two levels of programmable in-memory logic computing units were used.Furthermore,this design,built upon the proposed in-memory logic computing architecture,successfully realized an 8-bit KoggeStone adder and a 4-bit Wallace multiplier,surpassing previous works in terms of mapping complexity and computational complexity.In conclusion,the research presented in this dissertation on key technologies for processing-in-memory chip designs,including the in-memory reservoir computing architecture,on-chip unsupervised learning-based processing-in-memory architecture,and the non-volatile SRAM programmable processing-in-memory architecture based on resistive switching memory(RRAM),holds the promise of providing insights towards achieving more stable,energy-efficient,and versatile processing-in-memory architectures.These advancements pave the way for potential breakthroughs in the field of processing-inmemory,with the potential to enhance stability,energy efficiency,and applicability in a wide range of applications.