The Circuit Design Of In-memory Logic Operation And CAM Based On 10T SRAM

The growth of artificial intelligence and other technologies has inadvertently enriched our lives,but it also declares new challenges to system design in the aspect of computing speed and energy consumption.Obviously,due to the separation of memory modules and computing units in hardware,the conventional computing architecture has become harder to achieve the speed and energy requirements of these emerging applications,and the von Neumann bottleneck has thus formed.Computing in-memory(CIM),as a new computing architecture with great potential in the future,aims to solve the problems caused by the von Neumann bottleneck.It does not require frequent data transmission between the storage module and the computing unit,thereby efficiently improving the computing speed and reducing energy consumption.Besides,static random-access memory(SRAM)is highly commercialized and has the attributes of high stability,low energy,and high speed,so it is one of the foremost research objects of computing in-memory.This thesis proposes a new type of 10 T SRAM cell,which is mainly composed of three parts,which are the memory module composed of two coupled inverters,the write path composed of two access transistors,and two decoupled read ports.The cell can realize the separation of reading and writing.Besides the dedicated writing line,the cell is also equipped with cross-layout double word lines,giving the new SRAM two read modes: row-wise read mode and column-wise read mode.In addition to the basic SRAM mode,the proposed 10 T SRAM can also achieve bidirectional in-memory Boolean logic operations by activating multiple rows or columns.Besides,by properly configuring signal lines,sense amplifiers(SA),and decoupled read ports,the proposed 10 T SRAM can also be configured as a bidirectional content-addressable memory(CAM)to implement parallel data search operations,and the symmetry of the structure provides two alternative data search methods,namely,search by column or search by row.Both the in-memory logic operation and the CAM search operation are realized through the decoupled read ports,which avoid the direct connection between the storage node and the external circuit during the computing process and ensures the stability of stored data.The design uniquely proposes a bidirectional and symmetrical in-memory computing model,especially CAM search,which gives the system flexibility and can adapt to different application scenarios such as high-speed cache and IP router.The proposed SRAM has been achieved functional verification and manufacturing in 28 nm CMOS technology,with a capacity of 64 × 64(4 Kb).The results indicate that the 10 T cell achieves a 3× higher read static noise margin compared to the conventional 6T SRAM cell.At the voltage of 0.9 V,the frequency and energy consumption of logic operations are approximately 370 MHz and 15 f J/bit,respectively,and the BCAM search operating frequency is approximately 333 MHz and the energy consumption per bit is approximately 1.02 f J.