Design On Circuit Architecture Of Product And Dot- Product Based On SRAM

Artificial intelligence have been developed rapidly in recent years.Related applications,such as voice and image recognition,target detection,etc.,have huge requirements for computing,storage,and fast data exchange.The traditional bus structure,namely the von Neumann structure,physically separates the computing unit from the storage unit,which severely limits the performance of these applications and greatly increases power consumption.Therefore,computing in memory is naturally proposed.It can not only store data as normal memory,but also can accomplish some computing operation in-situ.Computing in memory can greatly enhance the computing speed and data throughput,and decrease power consumption dramatically.Because it goes beyond the bus structure.Because Static Random-Access Memory(SRAM)serves as the cache of the CPU,it has many advantages,such as fast speed and low power consumption.So SRAM has always been the focus of computing in memory research.This paper proposes a novel product and dot-product calculation circuit structure based on the SRAM standard 6T cell array.The main work of this paper is as follows:First,this paper introduces the background and the research status of computing in memory at home and abroad,and then explains the circuit structure and working principle of SRAM in detail.At present,many computing in-memory circuit structures based on SRAM have been proposed already.Three of them are selected for analysis and explanation in this article.Second,this paper propose a novel product and dot-product calculation circuit structure based on the SRAM standard 6T cell array.Since the traditional 6T cell structure has not been changed,the circuit structure can still be used as a general memory.The main principle of the product and dot-product calculation circuit structure is to store the multiplicand in binary form from low to high in a column of cells,and then generate pulse signal by pulse width modulation.The acting time of the pulse signal represents different weight.While the multiplicator is input from low to high in binary form.The result of AND operation between the WLP signal and later operand decide that WLs are activated or not.After that,the local bit-line performs the multiplication operation according to the data stored in the column of cells.Finally,the local bit-lines implemented multiplication are connected to the global bit-line,and the dot-product can be performed on global bit-line via charge redistribution.In the process of multiplication,with the decreasing of voltage and discharge speed of local bit-line,it is inevitably to occur nonlinear problems.For this reason,we introduce a feedback circuit module based on the current mirror.The word line signals decide whether open the feedback circuit or not.The reference current of the current mirror is dynamically controlled by the local bit-line current,so that the discharge speed can be accelerated and the problem of nonlinear can be significantly improved.Third,in order to reflect the advantage of the proposed novel product and dot-product calculation circuit structure,this paper simulate and analyze the circuit performance,recognition accuracy,power consumption and other dimensions based on TSMC 65 nm CMOS technology.Finally,the integration nonlinearity is reduced from less than 12 LSB to less than 4LSB.In addition,the recognition accuracy of handwritten numeral recognition is only 0.26% lower than the ideal case.The highest power consumption and average power consumption are as low as 14.5uW and 10.6uW,respectively.