Research And Design Of High-Speed, Low-Power SRAM

With the development of microelectronics technology, memory devices have shown the developing trends toward large capacity, fast speed and low power. The static random access memory (SRAM), as a member of the memory device family, has made significant advances recently, and has been widely applied in computer, communication and high speed data exchange systems. Current data shows that the memory devices occupy a 35% part of the overall semiconductor market, while SRAM amounts up to 15% of the semiconductor memory sales. Furthermore, the SRAM market is continuously increasing at a 10% annual rate.. In this viewpoint, studying SRAM is of great importance both practically and theoretically.The access rate of SRAM is basically determined by the critical path from address input to data output. The critical path is mainly composed of the address buffer, decoder, memory unit, sense amplifier and output buffer circuits. Among them, the memory unit is the core part with relatively fixed structure, and its performance is usually determined by the current semiconductor processing technology. As a result, people always pay more attention to the peripheral circuits (such as decoder and sense amplifier) of SRAM in designs. Compensations must be considered among the speed, area, and power dissipation to achieve optimized values in SRAM designs.A 256Kb SRAM has been designed in this work. The structure and the working principles of the SRAM is introduced firstly, with an emphasis on, design of the memory unit, decoder, sense amplifier and hierarchical bit line. After analyzing the influencing factors of power dissipation and accessing rate of SRAM in detail, optimization measures are provided so that the memory performance can be raised by improving the structure of peripheral circuits. Finally, the memory system is simulated by Hspice and Hsim under 0.25μm CMOS standard process. The results show that the access time of the memory is less than 12ns under the normal work condition (V_Dd=2.5V, T=25℃). The parameters have met the designing goal. Hence, both the high speed and the low power are achieved in an equivalent process, which can be used as a useful reference for future memory designs.The thesis is divided into six chapters. The first chapter introduces the development and classification of the memory. The second chapter describes the working principle and the system structure of SRAM. The third chapter talks about the design and optimization of the critical circuits such as the decoder and the sense amplifier. Optimized design of the memory array is discussed in the fourth chapter. In the fifth chapter, the overall design and the simulation results are presented. The conclusion and the future of SRAM are given in the last chapter.