Study Of Mosfets’ Radiation Hardening In The Weak-current-signal Readout Integrated Circuit

The high-performance weak-current-signal readout integrated circuit(ROIC)becomes more and more important for its wide application in IRFPA(Infrared FocalPlane Array). The ROIC often works in total ionizing dose(TID) environments andoften doesn’t work normally because of the TID effects. So it’s essential to make theROIC TID-hardened. Cost would be reduced greatly if the hardening is achieved in thestandard commercial production line. The hardening way related to layout designingbelongs to this. Based on the above mentioned, the paper studies the hardening wayfrom aspect of layout designing to achieve TID-hardening of the weak-current-signalROIC.Firstly, the TID effects of MOSFETs and its influence on MOSFETs’ majorparameters are summed up. And it’s pointed out that the switching transistor in theCTIA ROIC turns to be sensitive for the increase of its off-state current in TIDenvironments.Secondly, several hardening layout structures proposed by others are discussed.And based on their hardening principle, three new TID hardening layout structures areproposed. They are annular-P-gate-cut structure,“+”-gate structure, and I-gate structure.Thirdly, the paper proposes a way using the “Insulator Fixed Charges” modelprovided by TCAD software to accomplish the simulation of the TID effects inMOSFETs and its applicability is confirmed by the practical simulation.Finally, simulation of the three proposed hardening structures are conducted byusing TCAD software. Simulation results obviously show that the variation of off-statecurrent and threshold voltage of MOSFETs based on the three proposed structuresbefore and after TID radiation is smaller than that of the unhardened MOSFETs(theforward drift of the annular-P-gate-cut structure MOSFET’s threshold voltage makes itmore effective to restrain the off-state current), thus proving that the three proposedhardening layout structures are capable of TID hardening.