Study Of Radiation Layout Hardened Techniques In 65nm Bulk CMOS 8-Transistor Latch

Nowadays,with the vigorous development of space activities, States come to realize the importance of the aerospace industry. Meanwhile, the progress of aerospace industry is also closely related to the integrated circuit. However, in the space environment, as the integrated circuit portion in spacecraft is susceptible to high energy particle radiation, it may cause single event effects and lead to errors or even damage to spacecraft. As we all know, latch is commonly used and accounting for the most of areas in integrated circuit unit, thus it easily affected by Single Event Effect.To study and solve the problem, this paper study about radiation layout hardened technology in 65nm bulk CMOS 8-Transistor latch. Analysis the effect of layout spacing on single event effect in detail and using Guard-ring for radiation hardening. Results show that it has good effect on 8-Transistor latch.The main work is as follows:First of all, this paper introduced the types of radiation particles and generation principle of radiation effect in detail. Then, described several hardened techniques mainly includes the layout hardened technology, circuit hardened technology and so on. After that, we use Synopsys Sentaurus TCAD tools to modeling the device physics models, which including single PMOS and NMOS, inverter and 8-Transistor latch. For studying the characteristics of devices in the radiation environment, we use the inverter and 8-Transistor latch to have radiation experiment on ionizing particle with different LET(Linear Energy Transfer). In addition, we also have radiation experiment on ionizing particle with normal spacing and smaller one to study the effect of spacing between adjacent devices on the Single Event Effect, in this paper. And then, determine the appropriate spacing for radiation hardening. Finally, this paper using Guard-ring on 65nm bulk CMOS 8-Transistor latch for radiation hardening and having a radiation experiment on 8-Transistor latch with Guard-ring in TCAD model. We use the hybrid model of 8-Transistor latch withTCAD physical models and HSPICE models for simulation, with and without Guard-ring. Result show that this design has good effect and easily conducted. It can provide references to the design of radiation hardening on 8-Transistor latch.