Research On Nonvolatile Average 7T1R Static Random Access Memory Based On RRAM

As the semiconductor industry continues to grow,MOS transistor size continues to shrink due to rapid increase in manufacturing processes,but the ever-shrinking size led to more stringent requirements on the deviation of manufacturing process in circuit for SRAM,and more sensitive for process fluctuations,the performance is more unstable too.However,the demand for high-speed,high-performance and low-power SRAM is increasing.In order to meet the market demand for low power consumption,the supply about reducing voltage technology has been proposed,but reduce the voltage will cause the static noise margin to reduce and the SRAM stability to further reduce.With the increasing of the number of SRAM cells,the leakage power consumption of SRAM in the static hold state can't be ignored.Especially for some systems that often shut down,when the leakage power consumption is much greater than the dynamic power consumption,reduce the leakage power consumption is essential to increase battery life.Moreover,For the traditional SRAM,the stored data will disappear when the system power is off,when the system power is on again,the information stored in the SRAM is random,and can not restore the data stored before power-down,which is undoubtedly not allowed for the application system that need to save a large number of field data and all kinds of system parameters.Although nonvolatile memory has the ability to save data after power-down,it can't replace the advantages that high speed,high performance and low power consumption of SRAM.In order to preserve the advantages of SRAM on chips,many chips use "two-macro" which contains both volatile and nonvolatile memory,when works normally,it works in the same way as SRAM,SRAM data is stored in nonvolatile memory at power-down,and SRAM data is written back to SRAM by nonvolatile memory at power-up again.SRAM power-down information storage is maintained while SRAM high-speed,high-performance and low-power advantages are retained.The method uses word-by-word to transfer data between volatile and nonvolatile memories.Power-down storage and power-on recovery data are slow.Long power-down and power-up times not only reduces speed and may cause data errors.In order to reduce the power consumption of SRAM and complete SRAM power-down data storage,several nonvolatile SRAMs(Non-volatile SRAM)are proposed based on the resistive random access memory(RRAM).These advantages and disadvantages of several schemes are analyzed and compared by simulation.Firstly,the driving transistor size can be adjusted to achieve a predictable state of SRAM at power on.The scheme increases the size of each cell,and compared with the traditional 8T2R structure,the area reduction is not obvious,and the recovery rate is lower.And then proposed to interrupt the SRAM discharge path to achieve predictable state of SRAM,the scheme saves a lot of chip area,write ability significantly improved,but the rate of recovery is low too.The final scheme proposed significant improve in all aspects of the performance.The resistor nonvolatile memory cell consists of seven transistors and a resistive random access memory,it contains a non-volatile memory(1T1R)and a standard 6-transistor SRAM cell,and each column in the nvSRAM plus an NMOS transistor constitute the nonvolatile average 7T1R nvSRAM(NVA-7T1R)proposed in this thesis.Compared with the existing several nvSRAM,the NVA-7T1R has small area,fast speed,low power consumption,strong ability to read and write and other advantages.Increased transistor for each column greatly improves cell write capability,which is nearly one times the write capability of conventional SRAM.During the data recovery phase,the SRAM data recovery speed of NVA-7T1R is nearly 2.5 times faster than the previous 7T1R structre and the cell DC power consumption is reduced by 63%because of breaking the latch of the SRAM coupled inverters.