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Research And Circuit Design Of Ultra Large Array CMOS Image Sensor

Posted on:2020-09-01Degree:MasterType:Thesis
Country:ChinaCandidate:D Z ZhangFull Text:PDF
GTID:2518306518469264Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of standard CMOS technology,CMOS image sensors have gradually occupied the mainstream market for their low power consumption,low cost and simple structure.Resolution is an important performance index for CMOS image sensors.A higher resolution means that the details of the captured image are richer,so it is widely used in high-end industrial inspection,ancient painting identification,satellite photography and military industry.Whereas,the higher the resolution,the larger the pixel array,resulting in an excessive chip area,so that the length of the timing signal line and the column bus is too long and the parasitic effect is serious.In this paper,theoretical analysis and mathematical modeling are carried out for this non-ideal effect.The corresponding circuit design,layout design and chip test are completed.Firstly,the influence of column bus parasitic effects on the noise characteristics and response speed of pixel output signals is analyzed in this paper,and the simulation verification is carried out.The data show that the increase of the column bus width will cause output noise reduction and a longer response time under a given pixel array.Then,an optimized design scheme of the column bus is given according to the relationship between the noise characteristics,the response speed and the column bus size.Finally,the circuit design of a large array CMOS image sensor is completed in 110 nm CMOS technology based on the pixel structure analysis,ADC integration scheme analysis and architecture analysis.The core circuits include correlated double sampling,analog-to-digital converter,bandgap circuit and on-chip temperature sensor.And the 2K×2K CMOS image sensor is taped-out and tested.After simulation: for a 12.45cm×12.45 cm large pixel array,the 0.5?m column bus width can be used to achieve the compromising effect between pixel output noise and response speed.The average output noise of the pixel array is 146?V and the average drop time is 6.35?s.The sample sensor was tested,the row period is 24.36?s,and it can achieve a frame rate of about 19 frames per second at full resolution imaging.
Keywords/Search Tags:Large array CMOS image sensor, Correlation double sample, Parasitic effect, Column bus
PDF Full Text Request
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