Design Of A High-speed Column-level ADC For CMOS Image Sensor

In recent years, with the development of CMOS process technology and IC design methodology, CMOS image sensor has been developing rapidly for its advantages of low cost, low power, high speed of read-out, easy to integrate etc., and it has been applied widely in many solid-state image fields. At present how to improve the performance of CMOS image sensor for various applications has become a hot spot for the research of CMOS image sensor.The main objective of this paper is the research of digitalization of CMOS image sensor. Based on these analysis, this paper presents several analog-to-digital conversion plans. With the analysis of these test results, this paper gains some useful results, which set up the foundation of future design of CMOS image sensor of higher performance. Based on these subjects, this paper has carried out several researches as follows:Based on extensive reading and studies of relevant literatures, firstly this paper describes the principle, implementation, types, structures and the domestic and foreign development of ADC in a CMOS image sensor in detail. Then the analysis and comparison of types of ADC is presented to show the advantages and disadvantages. Base on the requirements of CMOS image sensor system, this paper presents a 10-bit multiple-ramp single-slope ADC which could be used in column-level ADC for CMOS image sensor. The major structure, the working mode and the simulation results of the circuit are shown in this paper. The design of circuits adopts resistor-array two-stage conversion structure and high-speed comparators. The circuit design, simulation and layout design are achieved on the platform of Cadence. The proposed circuit is taped out by 0.5μm DPTM CMOS process. The simulation results show that the basic requirement is met.