Design Of CMOS Image Sensor System

CMOS image sensor is the technology based on CMOS process, making great progress in recent ten years. It samples, transmits, processes and exports images using integrated digital and analog circuits. Comparing to other image sensors, it has the benefits of high integration, low power, low cost and powerful function, and has broad prospect.The primary parts of a CMOS image sensor system are designed in this paper based on the application of optical mouse. It includes pixel array, correlation double sample(CDS) circuit, analog-to-digital converter(ADC) and bandgap reference.There are 16×16 pixel units in pixel array, and pixel unit is active pixel sensor. Pixel array is sampled in the row-by-row way, and the output is 3125 frames/s. The row samples in pixel array are transmitted parallelly to CDS, a 1×16 array. Every unit of CDS corresponds to a column of pixel units, storages the samples of sample phase and integration phase of pixel units, exports their differences, and hence cancels the fixed pattern noise(FPN). The outputs of CDS are transmitted seriesly to ADC, and the analog voltage is converted into digital signal. The ADC is pipelined, including a single-input/difference-output sample/hold circuit and nine stage subcircuits. The preceding eight stages are 1.5bits/stage, and the last stage consists of two comparators. Every input sample is converted into 18 bits binary signals, and these binary signals are converted into 10 bits binary signals through digital correction circuit. The ADC's sample rate is 1.33MHz based on the requirement of preceding circuits. Static simulation shows the INL and DNL are both less than 1LSB by inputing limit samples to ADC. Bandgap reference provides reference voltage for overall circuits. It using two parasitic PNP BJTs in CMOS process creats reference voltage independent of temperature and power supply by op amp feedback. The simulation of the bandgap reference using ideal resistents shows that It's precision is 16.6 ppm.The dynamic range of the sensor is increased by 2~N using multi-sample. The FPN is cancelled using CDS. The pipeline ADC has the good tradeoffs of resolution, sample rate and area. The simulation shows that the performance of designed transistor-level circuit accords with theapplication requirements.