Design And Verification Of The Multiplier Based On PowerPC

This thesis studies the multiplier of X-type microprocessor, which is based on Power PC architecture. The reason why choose the Power PC architecture mainly comes from the flexibility of the structure itself. This flexible architecture can not only provide more price and performance combinations, and maintain software compatibility at the same time, but also make subsequent processors take better advantages of the development of the technology. The Power PC architecture is extendable, it also includes 32-bit and 64-bit implementation specification in order to ensure that the software is compatible between the current 32-bit Power PC processors and the next generation 64-bit processors.For processor, the operation unit is the crucial part which affects the performance of the processor directly and for operate unit, multiplier is the very important part of it. It is the core of digital signals management and logic calculation, improving the performance of multiplier has great meaning to microprocessor, so it’s necessary for us to study and design the multiplier.The X-type microprocessor is a superscalar microprocessor which has independent on-chip, 32-Kbyte, eight-way set-associative, physically addressed caches for instructions and data and independent instruction and data memory management units. It has a 32-bit address bus and a 64-bit data bus and supports single-beat and burst data transfers for memory accesses and memory-mapped I/O operations. In addition, it has four software-controllable power-saving modes and uses an advanced CMOS process technology and is fully compatible with TTL devices.This thesis studies a 32×32 bits integer multiplier, using the modified radix-4 Booth encoding. The result is achieved in five cycles. In each of the previous 4 cycles, 8 bits of the multiplier is encoded and four 34 bits partial products are obtained. In the last cycle, only 1 bit is encoded to generate the partial product for MSB. With the use of Booth encoding, it reduces the number of partial products by half, greatly enhancing the speed of operation. In each cycle, every four 34 bits partial products are compressed twice with 4-2CSA and 3-2CSA compressors to get a 40 bits operand, using Wallace tree compression method. Then the lower 8 bits of the operand is stored in a special register and is not returned for addition. In the last addition operation, the higher 32 bits of the result is retained in a register and is to be transported to the 3-2CSA compressor through a feedback circuit, so as to be added with the lower 32 bits in the next cycle. After four cycles’ repeated operations, the 64 bits result is obtained. This method not only makes the multiplier much faster, but also saves the area of the circuit. The adder in use is a mixture of look-ahead adder and carry select adder. The 40 bits operand is divided by every four bits as one unit and 8 bits is additionally needed for selection purpose, then it is divided into 12 sub-units. It makes possible that two adders take advantage of respective strengths to reduce the computation time.Finally, we verify the design in module-level and system-level. According to the analyzing of the result, the designed circuits realize all the functions. The design also passes the pre-simulation and the post-simulation.