Design Of High Speed Multiplier

As technical level develops, IC design progresses in both the ways of higher speed and smaller area steadily. CPU is more likely to represent this trend for it is a typical product of IC design. To get a better performance of the whole target, we should optimize all the components of the CPU in all possible ways.Multiplier is an important component of the CPU. In the domains of multimedia application, image process and so on, plenty of multiplications in cycles make multiplier a significant part, which plays an important role in deciding the performance of the whole CPU. This paper is about to focus on improvement on speed as well as area, and present three designs of multipliers varied by data width: 16×16, 32×16 and 32×32 multiplier and their actualization.First of all, the paper introduces the basic principle of multiplier briefly, and then figures out the modified radix-4 Booth algorithm in conditions of signed multiplication and unsigned multiplication separately. The number of partial product can be reduced to half of the number by original Booth algorithm, which decompresses the follow steps.After that, tree structures of the compressors considering both the parallel calculation and the balance of time delay are presented, which can improve the speed of multiplication effectively. In condition of high speed, the paper also gives three methods to reduce the number of adders in compressor in order to optimize the area. Then, we finish the design by using a grouping CLA.Verifications of the whole design show that the designs are right at RTL level. For actualization, we uses smic0.18 technical library to build the multipliers, and optimize them by using DC, which then pass the post-synthesis verification.At last, the paper analyzes the projects of accomplishing the same goal: 32×32 multiplication using three kinds of multipliers by the consideration of area and speed complexity, and figure out the optimized project.