Design And Application Of Binary Multiplier Based On Approximate High Radix Booth Encoding

As an emerging technology that can reduce circuit power consumption and improve circuit performance,approximate computing technology can be widely used in multimedia signal processing,artificial neural networks,cloud computing and other fields that contain a lot of data processing but do not require accurate results.Compared with the traditional full-precision calculation,the approximate calculation reduces the circuit complexity by introducing certain error in the calculation result.In the design of digital signal processing system,the design of the arithmetic units determines the energy efficiency of the whole system,and the multiplier often becomes the bottleneck of the system due to its complexity.Therefore,the introduction of approximate computing technology into the multiplier design will improve the energy efficiency and performance of the entire digital signal processing circuit system.This thesis introduces approximate computation into high radix Booth encoding and applies it to binary multiplier design.Basic principles of Booth encoding are introduced in this thesis to points out the characteristics of accurate high-radix Booth encoding,and a new approximate high-radix Booth encoding based on accurate high-radix Booth encoding is proposed.It is applied to the design of binary multiplier,the error model and circuit model are established,and the hardware performance and error metrics of the multiplier are simulated and analyzed.The proposed binary multiplier based on proposed approximate high-radix Booth encoding is applied to finite impulse response(FIR)digital filter to process the sound and image signals separately to evaluate its practical effect and application value in in errortolerant digital signal processing system.To solve the problem that the calculation of hard multiples in accurate high-radix Booth encoding is too complicated,the encoding results are approximated in this thesis,so that all partial products can be generated by shifting and negating operations.At the same time,to reduce the error introduced by the approximate,the encoding results of the approximate high radix Booth encoding are split to make it as close to the exact encoding result as possible.In the proposed approximate multiplier,the proposed approximate high-radix Booth encoding is hybridized with exact radix-4 Booth encoding.The approximation efficiency is calculated by the error model and the circuit model to obtain the optimal solution under different multiplier bit widths.The binary multipliers with16×16 and 20×20-bit widths are taken as examples.Simulation is carried out to verify the theoretical analysis conclusions.The approximate high-radix Booth encoding proposed in this thesis significantly reduces the hardware complexity of the encoding circuit and the partial product generation circuit.When it is applied to the binary multipliers,an efficient trade-off between multiplier accuracy and hardware performance is achieved and approximation efficiency is improved.When applying the binary multiplier based on approximate high-radix Booth encoding proposed in this thesis in the FIR digital filter and performing digital signal processing,the hardware performance of the system is significantly optimized,and the output signal is still acceptable.Therefore,the proposed approximate high-radix Booth encoding significantly improves the hardware performance of binary multipliers,and it shows better reliability when applied to the error-tolerant applications.