6.25Gbps SerDes Transmitter Design Based On 65nm Process

With the continuous improvement of communication technology,data transmission is greatly increased,in order to convey more information in the shortest possible time,required transmission rate improved significantly.When the data transfer rate up to Gbps,and difficulties to be overcome too much to the more attenuation transmission line growing,interference between data and more serious,so that the bit error rate.Traditional parallel data transmission can not meet the high-speed data transfer,but the serial link transmission able to meet the demand for such high-speed transmission.SerDes transceiver is a typical serial data transmission.SerDes transceivers as a typical serial data transmission,the study of SerDes is more and more important.Under the 65 nm process conditions,this paper design a SerDes transmitter which bit rates up to 6.25 Gbps based on the study SerDes transmitter theory.The input datas of the transmitter is 20-bit parallel data,output is a pair of differential data with programmable pre-emphasis function.The main work of this paper can be divided into the following explanation:1)Analysis and comparison of the advantages and disadvantages of three parallel-serial converter circuit structure,combined with paper designed transmitter transmission rate required to meet the design a way to meet the high-speed data transmission and serial conversion circuit;2)In order to ensure a 50% clock duty cycle,the duty cycle adjustment circuit are designed;3)For the degree of channel loss,and in order to overcome inter-symbol interference,the per-emphasis circuit are designed;4)To ensure the transmitter to transmit data at the receiving end is valid,design the receiver detection circuit.After the backplane transmission theory is analyzed in detail,designed SerDes transmitter circuit,layout and simulation,simulation results fully meet the PCIE protocol requirements.Transmitter output data rate can reach up to 6.25 Gbps,5Gbps,3.125 Gbps,2.5Gbps;output data amplitude can achieve 0.8-1.2V;eye hight can meet the requirements,eye width can achieve 0.9UI;jitter less than 0.1UI.