28Gbps SerDes TX Module Design Based On 28nm Technology

With the continuous improvement of semiconductor integrated circuit technology and communication technology,CPU high-density computing,dense image information processing,network information interaction and high-density data transmission all require higher and higher bandwidth of I/O interface and information transmission rate between different chips.The information transmission capability of signal transmission interface limits the system's ability to process data.Therefore,high-speed and undistorted signal transmission interface has become a hot research direction at present and in the future.When semiconductor technology enters deep sub-micron and nano-scale,the working speed of semiconductor devices and circuit systems also becomes faster and faster.Traditional parallel bus schemes are also facing many severe challenges due to serious signal offset and intersymbol interference.At the same time,when the transmission rate of the data signal reaches Gbps,the attenuation of the signal on the transmission line becomes more and more serious,which also increases the mutual interference between the data and increases the bit error rate.Therefore,in order to meet the requirements of high-speed signal data transmission,a high-speed serial interface SerDes(Serial-Deserial)is proposed to replace the previous design of data parallel.Based on UMC28 HPC technology,this paper studies and designs a SerDes TX terminal with a transmission rate of 28 Gbps.The main contents and work arrangements of this article are as follows:Since the 7GHz clock is fast,if the 7GHz four-phase clock is directly generated by the PLL,it is difficult to align the four-phase clocks after being transmitted to different lane,and the problems such as clock signal distortion and duty cycle distortion are difficult to solve.At the same time,PI module is also needed,which consumes a lot of power.TX doesn't need precisely aligned clocks at all.It can send data by aligning the single-phase clocks to a certain phase.Therefore,this paper designs a four-phase DLL(delayed phase locked loop)to divide a phase clock into four-phase clocks and collect data.Research and design the implementation of clock processing and parallel-to-serial conversion module.Due to the data transmission capability of 28 Gbps,the parallel-to-serial conversion module with CML(Current Mode Logic)structure under high speed is designed.The relevant currents of duty ratio detection module and duty ratio adjustment moduleare designed and implemented,so that the clock signal of collected data can maintain 50%duty ratio in parallel-to-serial conversion module.According to the characteristics of voltage-mode and current-mode drivers,a programmable pre-emphasis driver is designed and implemented in hybrid mode to effectively eliminate the inter-symbol interference of signal data during transmission.According to the layout rules,the digital module layout and the analog module layout in this paper are fully customized.