Design Of A 40Gb/s SerDes Transmitter Chip

With the continuous growth of the date transmission rates, the serial communication SerDes technology, which was used in the remote date transmission, is expending to other application area such as WAN/LAN and PC interface. Nowadays, the SerDes technology which has became the mainstream of high speed interface technology is widely adopted in all kinds of date communication systems. So the SerDes system has been extensively researched in recent years.Based on TSMC 65nm LP technology, a 40Gb/s SerDes transmitter chip is designed in this paper. The chip multiplexes four parallel input 10Gb/s date into one serial output 40Gb/s date with the requirement of less than 0.1 UI date jitter, and the reference clock frequency is 625MHz.The SerDes transmitter chip is composed of a MUX module and a PLL module. The direct 4:1 multiplexer architecture is adopted in the MUX module to solve the timing problem encountered in the traditional tree architecture multiplexer. Because the output date rate is too high, the bandwidth of the normal differential pair is not wide enough. The inductance peaking technique is used to broaden the circuit bandwidth. The PLL module adopts the charge-pump phase-locked loop architecture. In order to increase the transconductance and simplify the resonator design, the VCO uses the complementary cross-coupled negative resistance LC-VCO structure. After making a trade between speed and consumption of the circuit, the divider chain uses the current-mode logic(CML) divider in the first stage and adopts the TSPC architecture in the last four stages. The D flip-flop structure of the phase frequency detector is modified to decrease the width of the PFD inherent pulse without use of an And gate. The charge pump adopts the cascode structure and dummy transistors to match the charging and discharging current and to decrease the impact of charge injection and clock feedthrough.This paper completes the circuit and layout design of the SerDes transmitter chip. The post-layout-simulation results show that the eye diagram opening of the output date is ± 180mV and the jitter is less than 0.1UI. With the 625MHz reference clock, the PLL can be locked and operates at 20GHz. The whole chip consumes 125mW and occupies an area of 565um*702um.