Research On High-speed On-chip Interconnect Circuit Based On Time-domain Modulation

Three-Dimensional Network-on-Chip(3D NoC)has become the main research direction in the NoC field due to its advantages of high communication bandwidth,high packaging density and low power consumption.However,the heat dissipation characteristic of threedimensional integrated circuits has limited the improvement of communication speed and power consumption performance of highperformance 3D NoC.On-chip high-speed low-power interconnection technology provides a feasible solution to speed and power bottlenecks.This paper studies the high-speed and low-power interconnection technology and circuit design in 3D NoC.According to the process shrinking and evolution,the time domain signal has higher resolution than the voltage domain.This paper develops high-speed and low-power interconnection circuits based on time-domain signal transmission.First,after studying the existing high-speed signal transmission technology in the time domain,an all-digital high-speed interconnect structure design based on time amplification and time-digital conversion is proposed.Secondly,for the pivotal time amplifying circuit,this paper proposes an improved amplifier structure.By redesigning and optimizing the control circuit and the delay chain based on the tri-state inverter,the goals of high time resolution and high linearity are achieved.Third,based on the highprecision time amplifier,the coarse TDC,fine TDC,MUX and output decoder are optimized,and a high-resolution time-to-digital converter is designed.Finally,based on the improved module,this paper completes the design and optimization of the transceiver circuit.Aiming at the problem of the duty cycle distortion of the transmitting end signal,this paper reduces the impact of the duty cycle distortion on the system reliability by inserting buffers and adjusting the update time of the input binary data.This paper completes the transceiver circuit design and Spectre simulation based on SMIC 40 nm CMOS process.The simulation results show that the transceiver circuit structure designed in this paper achieves a data transmission rate of 6Gbps in the TSV channel,and it can be applied to on-chip 9mm interconnect lines for 4Gbps data transmission.Compared with similar designs,this circuit structure has lower power consumption,and the energy consumption per bit transmission is 68.75 f J/bit/mm.The high-speed transceiver circuit structure proposed in this paper has the characteristics of low power consumption,easy expansion and portability.At the same time,it can be realized by all digital circuits and is expected to be applied to 3D NoC interconnection.