Research And Design Of Highresolution Time-to-digital Converter

Precise time measurement plays a significant role in some large physical experiments,defense and industry fields,as the basic device of time measurement,the resolution of time-to-digital converter(TDC)directly determines the function and performance of its application.On the other way,digital integrated circuits highlight a number of advantages over analog integrated circuits in deep submicron processes,there are more and more circuit systems implemented with digital circuits,since TDC can convert successive timedomain signals into digital signals,it will serve as one of the key modules in some integrated systems under deep submicron processes.Because the resolution of TDC is a key factor affecting system performance in time measurement and digital systems based on TDC,the research and design of high-resolution TDC is of great significance.This paper targets to design a high-resolution time-to-digital converter,a highresolution time-to-digital converter is implemented using a pipelined architecture on the basis of in-depth research and analysis of the advantages and disadvantages of different structures on the high-resolution TDC.In this paper,the time storage technology is analyzed and realized by circuit,which makes it possible to realize pipeline structure,the digital correction algorithm is designed to reduce the adverse effect of offset error on TDC measurement.The TDC consists of clock circuit,pre-processing circuit,three 2.5b/stage TDCs,a three 3b delay-line TDC and digital error correction circuit.In the pre-processing circuit,a pulse generator is designed to converts the input to a pulse;in the 2.5/stage TDC,a sense amplifier-based flip flop with narrow metastable window is designed to avoid "bubble" in the thermometer code output from the sub-TDC,which can affect the overall measurement result of the TDC,in order to overcome the shortcomings of the traditional time amplifier,which magnification is inaccurate and difficult to control,a novel time amplifier is adopted to amplify the quantization margin precisely so that the input of the post-stage circuit is correct.A digital error correction circuit is designed to process the binary output from per stage and a 9-bit digital output can be obtained.The circuit and layout of the pipeline TDC is implemented with SMIC 0.18?m CMOS process,the area of the core circuit is 415?m×217?m,the simulation results show that sampling rate is 50MS/s,resolution is 4.62 ps,dynamic range is 0~2348ps.