Design And Realization Of Time-to-digital Converter Based On Time Amplification Technology

In recent years,high-performance three-dimensional imaging technology has attracted people's attention due to the huge demand in engineering,science,medicine and entertainment field.In 3D applications,such as robotics,biometrics,and security monitoring,it is necessary to extract 3D depth images of two-dimensional images and scenes simultaneously.Therefore,how to realize high-precision and highly-efficient measurement of distance information has become the key of development of 3D imaging technology.One of the most advantageous methods for 3D imaging distance measurement is the direct time-of-flight ranging method,whose principle is that the light source emits continuous pulsed light to the target object,and then uses the sensor to receive the pulsed light reflected from the target object.Under the premise of known light speed,the pulsed light travel time is used to calculate the distance information of the target.In practice,the distance information is obtained through the corresponding measuring circuit.Thus,it is of great significance to research the time interval measurement circuit by using the direct flight time ranging principle in-depth.This thesis focuses on the research of time to digital converters based on direct flight time ranging technology.The purpose is to achieve the 3D ranging chip's performance requirements for high accuracy,high integration,low power consumption,low cost,and portability.This paper initially elaborated the working principle of various time to digital converters,followed by a detailed description of their basic structures and performance indicators,and finally selected two-step time digital sensors based on Time Amplifier(TA)for further study.This thesis uses SMIC 180 nm CMOS process and selects a single photon avalanche photodiode(SPAD)as a photon detector.It is used a direct time-of-flight distance measurement principle to design a novel time amplifier based two-step time to digital converter pixel readout circuit,eventually completed the monolithic integrated layout design.Among them,the pixel readout circuit includes a quench circuit,an interface circuit,a coarse counter,a data selector,a time amplifier,a fine interpolator,and two encoders.The two-step architecture guarantees a wider timing range and fine time resolution without the need for additional calibration.In addition,the method of residual pulse time difference amplification helps to reduce the quantization error and ensure a reasonable chip area and power consumption.In this paper,the designed pixel area is 100*200?m2,the number of bits is 6bit,the frequency of reference clock is 300MHz,the dynamic range of 128ns and the time resolution of 52ps are realized,and the differential non-linearity(DNL)of ±0.50 LSB and integral non-linearity(INL)of ±0.76 LSB are achieved respectively,and the timing offset error does not exceed 1.85%.