A Time-Domain All-Digital PLL Design

In this paper, a time-domain all-digital phase-locked loop (TD-ADPLL) model structure is proposed, and a complete circuit development process flow is demonstrated also. Comparing with the traditional PLL, its entire loop system is achieved by the digital blocks. Moreover it takes full advantage of characteristics of digital circuits, and deals with the binary digital signals directly in time-domain in the loop, making the architecture more compact and efficient. In this structure, the digitally controlled oscillator (DCO) and time-digital converter (TDC) share a free-running ring oscillator's (FRO) outputs as a multi-phase reference signal, so the product of conversion resolution is fixed to 1, which implies the loop stability independent of the variations of the process, supply voltage, the ambient temperature. Use a binary digital shifter replace the traditional divider in ADPLL, make the structure simple and keeps the loop gain constant when the frequency multiplication factor changes. The loop theoretical analysis shows that the damping and bandwidth of the loop transfer function only depends on two factors of the digital loop filter. It can be seen,this all-digital phase-locked loop structure has a large input and output frequency range, and a large frequency multiplication factor range, as well as a good tolerance for the variation of the supply voltage, temperature.The proposed ADPLL is fabricated applying 0.13μm standard CMOS digital logic process in Semiconductor Manufacturing International Corporation (SMIC), and the whole chip area is 0.09 mm2. The test results show that the time-domain all digital phase-locked loop functions well under input frequency range from 50 KHz to 25 MHz, frequency multiplication factor range from 16 to 255, the output frequency range from 50 MHz to 500 MHz, power supply voltages from 0.6V to 1.6V, which is consistent with the theoretical analysis, can be easily integrated into many electronic systems.