Design Of Hybrid Time-to-Digital Converter Based On Residual Time Amplification

Time measurement is widely used in the fields of scientific research and engineering. It has occupied a crucial status in telecommunications, military, aviation, atomic physics, etc. Time-to-digital converter (TDC) is applied for measuring time intervals between two asynchronous pulses. It utilizes various structures of different patterns to convert the input time into a digital code. Compared with ADC, TDC can be considered as a specific case of ADC and it facilitates the time direct conversion with the unique advantages of simple structures, low hardware resource consumption and high reliability. Consequently, TDC has gradually substituted ADC to become the best choice for time measurement.This thesis proposes a novel hybrid TDC architecture based on the residual time amplification, which combines the advantages of both multi-stage TDC and multi-step TDC to measure wide-range time precisely. In the circuit, a two-stage TDC is utilized to complete the coarse measurement, which contains a counting TDC of the high-level and an oscillator-based TDC of the middle-level. The two-stage TDC mainly extends the full range and achieves relatively high resolution. Its residual time is extracted by the remaining time extraction circuit. Subsequently, a two-step TDC cored on the time amplifier linearly amplifies the extracted residue. The time amplifier uses the variable-gain structure based on delay locked loop (DLL), which provides a wide linear input range and stable gain for the two-step TDC. A tapped delay-line TDC is employed to fulfill the measurement of the amplified time, where the delay-line TDC employs the same delay units as the middle-level TDC. The two-step TDC works in the "amplify-requantify" manner, achieving the resolution of the TDC system beyond the minimum gate delay due to the CMOS process. Besides, the proposed TDC utilizes the DLL to generate the counting clock, which effectively improves the stability of the oscillation clock and delay elements by the negative feedback characteristics.The circuit is designed and fabricated in TSMC 0.35?m CMOS process. Also, the layout design, simulation and tape-out are completed. The test results show that at 3.3V supply voltage and under room temperature 27?, the proposed TDC achieves a resolution of 320ps, a full scale of 2.551?s, DNL of ±0.68LSB, INL of-1.23LSB-1.19LSB and Single Shot Precision(SSP) of 0.73LSB, and consumes 10.9 mW from a 3.3V voltage supply, which meets the design requirements.