Physical Design Of Low-power IOT Node Chip Research And Implementation

Due to the rapid development of the Internet of things,the large-scale development of Internet of things node chip has become inevitable.Each IOT connected device can be regarded as a node,and each node contains at least one IOT node chip.Therefore,the integration and scale of IOT node chip will increase dramatically.With the increase of integration and scale of IOT node chip,power consumption will inevitably occur.In the design of low-power ASIC,we need to consider the logic design of the front-end and the physical design of the back-end.The front-end low-power logic design provides a theoretical basis for the overall design of low-power.Through the analysis of the physical characteristics of power consumption to achieve power estimation;through the low-power theoretical basis provided by the front-end,combined with the actual physical design rules and methods,the low-power logic design of the back-end realizes the low-power layout design.How to reduce the power consumption of the Internet of things node chip from the chip back-end design,solve the power consumption problem caused by the increase of chip integration and scale,so as to carry out system level low-power design for specific Internet of things node chip,is the main research content of this subject.In this paper,the low-power design of IOT node chip is studiedThis paper analyzes the physical design process and power consumption of digital integrated circuits,and investigates the physical design of low-power digital chips commonly used in the industry.At the same time,the gate clock technology is used to design low power consumption in the synthesis stage.The gate clock technology is adopted.In the process of logic synthesis,the enable signal is added to the clock,so that the input section of the clock signal is turned off when the register state does not need to be changed,so as to avoid the redundant overturning of the clock signal and reduce the power consumption.The logic synthesis of IOT node chip is carried out,and the comprehensive results are compared with those without low power consumption.The physical design of IOT node chip is carried out.Based on TSMC 0.18 ? m,the physical design of IOT chip is carried out,and the power consumption is optimized by changing the topology of clock tree.Control the growth of clock network topology structure to make it more horizontal expansion,so as to reduce the clock network power consumption and optimize the clock network area.The physical design results of this project show advantages in clock tree power consumption.In this paper,gate clock technology and clock tree topology optimization are applied to the design of IOT node chip.The research in this paper has a certain reference significance in the specific chip low-power design.