Physical Design Of A Low Power Digital Baseband Processor For UHF RFID Tag

Radio Frequency Identification(RFID)is a kind of wireless communication technology.It can identify specific targets by radio signals and complete the reading and writing of related data.It does not need to establish mechanical or optical contact between the recognition system and specific targets.Compared with other identification technologies,radio frequency identification technology has the characteristics of high speed,long distance,high flexibility and high data density.Therefore,in recent years,radio frequency identification technology has been widely used in finance,logistics,transportation,anti-counterfeiting,certificates and other fields.It is also one of the supporting technologies of data acquisition in the Internet of Things.It has a huge market and bright prospects.At present,the development of radio frequency identification technology is restricted by two main problems:one is the power consumption.For passive tags,the energy required for their work comes entirely from the radio frequency energy emitted by the reader.In practical applications,tags often get only hundreds of microwatts of energy,which is greatly limited.If the power consumption of the chip is too high,The energy obtained from the RF energy emitted by the device is very limited,which will greatly shorten the identification range of the tag chip.The second is the cost problem.Compared with other identification technologies such as barcode identification,the cost of the RF identification equipment is much higher,because the RF identification technology needs to place the tag chip on each identified target.So it is very important to find the technology to reduce the cost of label chip.In view of the above situation,this paper makes a detailed study of the power consumption in integrated circuits,analyses the mechanism of various power consumption,and studies the current low power technology,then uses clock gating technology to optimize the power consumption of the design,and then synthesizes the design with low power clock tree,and carries out the parameters and structure of the clock tree of this design.At the same time,an algorithm is designed to reduce design congestion in the layout stage,which can optimize the total wire length,timing,congestion and other key parameters of the chip,and use TCL scripting language to implement it.Finally,it is applied in the back-end physical design of the design,which improves the utilization of the chip layout.In the layout stage,we use the congestion optimization algorithm designed in this paper to further optimize the layout results,further reduce the area of the chip and reduce the cost of the chip.Finally,we verify the design from two aspects of physical layout design and post-simulation to ensure the final layout.Effectiveness.The chip designed in this paper uses the SMIC 65nm standard cell process,with a power supply voltage of 1.2v,a layout size of 109.4 ?×108 ?m,an area of 1185 ?m2 and a power consumption of 6.936 ?W.The design has validated from three aspects:layout vs schematic,design rules check and electrical rule check,then the design has passed the post-simulation.The verification shows that the physical layout of the design meets the design requirements and ensures the validity of the final layout.