ASIC Backend Physical Design Based On FINFET Process

With the decreasing of the feature size of the semiconductor technology, the device has the increasing problems of short channel effect which will lead increase of leakage current in sub-threshold and reduce of the threshold voltage.All those bad effects will lead to results of high power-consuming and bad performance of the chip. In recent years, in order to achieve good performance and low power-consuming, TSMC and Samsung has developed FINFET technology of 16/14 nm. As the bridge of chip design and manufacturing, the backend physical design is particularly critical. This paper's research topic is based on a FINFET backend physical design process.This paper describe a physical design of a module which is in Graphic Processing of Accelerated Processing Unit, through using streamline design software and EDA tools. This paper's purpose is to get the best scheme of the layout based on the different macro planning with the heat map of cell pin density and the result of utilization,congestion and timing. What's more,this paper also get the power planning of the module by the result of calculation and the analysis of IR drop and electro-migration. At the stage of placement, the special physical cell and the standard cell are inserted to the module and get the placement result of congestion and timing.At the stage of CTS, this paper get the best clock skew scheme by comparing the different clock skew experiment, analysis of the result,experiment of congestion, route DRC and timing. After the routing, we fix the route problems by considering FINFET design rule to meet the design requirements. Then we also analyze antenna issue, Via resistance and reliability problem and get the related fixing methods. In order to achieve low power design requirements, the paper defines the power switching gate in UPF file to implement power off technology which generate ONOFF and Always ON power domain in power grid. In order to meet the design rules of double pattern technology in the design, this paper come up with a polygon cycle method to check rule and find the method to fix metal layer with DRC violation. This paper get the sign-off timing through the experiments, and fix the violation of transition, max load capacitance, setup time and hold time. After fixing all the violations, the design meet the requirements of sign-off.